Introduction to DDR SDRAM

Bill Gervasi Technology Analyst [email protected]

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Topics to Cover

• The SDRAM Roadmap • Transitioning from SDR to DDR • DDR-I 400 Overview • Market overview 2

SDRAM Evolution

5400MB/s

Mainstream Memories

4300MB/s 3200MB/s 2700MB/s

“DDR II”

2100MB/s 1600MB/s 3200MB/s 1100MB/s

“DDR I” “SDR”

Simple, incremental steps

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Key to System Evolution

• Never over-design!

• Implement just enough new features to achieve incremental improvements • Use low cost high volume infrastructure – Processes – Packages – Printed circuit boards 4

From SDR to DDR

Differential Clocks Write Latency Signaling & Power Data Strobe 5

Prefetch

• Today’s SDRAM architectures assume an inexpensive DRAM core timing • DDR I (DDR200, DDR266, and DDR333) prefetches 2 data bits: increase performance without increasing core timing costs • DDR II (DDR400, DDR533, DDR667) prefetches 4 bits internally, but keeps DDR double pumped I/O • DDR-I 400 is a prefetch-2 architecture 6

Prefetch Depth

CK

data READ

SDR: Prefetch 1 Core access time

Costs $$$

DDR-I: Prefetch 2 DDR-II: Prefetch 4 Column cycle time

Essentially free Costs $$$ 7

Prefetch Impact on Cost

SDRAM Family SDR DDR-I DDR-II Pre fetch 1 1 2 2 2 2 4 4 Data Rate 100 133 200 266 333 400 400 533 Cycle Time 10 ns 7.5 ns 10 ns 7.5 ns 6 ns 5 ns 10 ns 7.5 ns High Yield = Affordable Starts to get REAL EXPENSIVE!

Comparable to DDR266 in cost

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DDR Data Timing

• Data valid on rising & falling edges… “Double Data Rate” • Source Synchronous; Data Strobe “DQS” travels with data 9

From SDR to DDR

Prefetch 2 Write Latency Signaling & Power Data Strobe 10

DDR Clocks

• Differential clocks on adjacent traces • Timing is relative to crosspoint • Helps ensure 50% duty cycle 11

Single Ended Clock

CK Normal balanced signal Clock high time Clock low time V REF V REF CK Mismatched Rise & Fall signal

Error!

Clock high time Clock low time

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Differential Clock

CK CK CK CK Normal balanced signal Mismatched Rise & Fall signal Clock high time Clock high time Clock low time Clock low time

Significantly reduced symmetry error

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From SDR to DDR

Prefetch 2 Differential Clocks Write Latency Data Strobe 14

DDR Signaling

• SSTL_2 low voltage swing inputs – 2.5V I/O with 1.25V reference voltage – Low voltage swing with termination – Rail to rail if unterminated 15

Power = CV

2

f%#

Factors: • Capacitance (C) • Voltage (V) • Frequency (f) • Duty cycle (%) • Power states (# circuits in use)

Keys to low power design:

Reduce C and V Match f to demand Minimize duty cycle Utilize power states 16

Power: SDR



DDR-I



DDR-II

12 10 8 6 4 2 0 PC-133 @ 3.3V

DDR266 @ 2.5V

DDR533 @ 1.8V

Throughput per Second per Unit Power

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From SDR to DDR

Prefetch 2 Differential Clocks Write Latency Signaling & Power 18

Emphasis on “Matched”

CONTROLLER DDR SDRAM DQ/DQS

V REF V REF

DM

V REF V REF Disable • DM/DQS loading identical to DQ • Route as independent 8bit buses 19

64 = 8 x 8

• 64bit bus is 8 sync’ed 8bit buses • Allows external “copper” flexibility • 8 buses resync upon entry to FIFO

Copper from controller to SDRAMs Sync to Controller clock

Inside Controller

x16 DDR SDRAM

8 DQ 1 DM 1 DQS 8bit Buffer 8 DQ 1 DM 1 DQS

x16 DDR SDRAM x16 DDR SDRAM

64bit Memory Controller Internal FIFO

x16 DDR SDRAM

8 DQ 1 DM 1 DQS 8bit Buffer 20

From SDR to DDR

Prefetch 2 Differential Clocks Signaling & Power Data Strobe 21

Write Latency

• SDR had to keep inputs powered all the time • Adding Write Latency to DDR allowed inputs to be powered off between commands • Flexible timing differences on data and address paths 22

DDR-I vs DDR-II @ 400

3200MB/s

“DDR II”

2700MB/s 3200MB/s

“DDR I”

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DDR-I 400 Summary

• DDR-I is hard to design to 400 MHz data rate – Lower yields • No JEDEC standard • Prefetch-2, 2.5V signals, TSOP packages, write latency 1 – DDR-II makes it a lot easier • JEDEC standards & focus • Prefetch-4, 1.8V signals, differential strobe • On-die termination, BGA packages, write latency > 1 • Same plane referencing • Few suppliers supporting DDR-I 400 market 24

DDR-I 400 Conclusion

• The JEDEC roadmap represents the industry focus for mainstream products – DDR-I tops out at 333 MHz data rate – DDR-II starts at 400 MHz data rate • This

DOES NOT

mean that DDR-I at 400 MHz data rate will not ship in volume • It

DOES

mean that there will be price premiums for this speed bin 25

Market Outlook

• DDR-I – DDR333 is the mainstream product for 2003 – DDR-I 400 will be the premium market • DDR-II – DDR-II designs under way now – DDR-II 400 & 533 will sample in 2003 – DDR-II ramp begins in 2004 26

Summary

• DDR has many improvements over SDR – Prefetch, differential clock, low voltage, data strobe, write latency • DDR-I 400 likely to stay a profitable niche • DDR-II volume products for 400 & 533 ramp in 2004 27

Thank You

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