Transcript DDR Evolution and Memory Market Trends

DDR Evolution and
Memory Market Trends
Bill Gervasi
Technology Analyst
[email protected]
Topics to Cover
 The
SDRAM Roadmap
 DDR-I & DDR-II Comparison
 Why DDR-I 400 is Boutique
 Memory Modules Changes
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DRAM Evolution
Mainstream
Memories
4300MB/s
5400MB/s
3200MB/s
“DDR II”
2700MB/s
2100MB/s
3200MB/s
1600MB/s
1100MB/s
“SDR”
“DDR I”
Is DDR-I 400 a
temporary blip?
3
Simple,
incremental
steps
Key to System Evolution

Never over-design!

Implement just enough new features to
achieve incremental improvements

Use low cost high volume infrastructure



Processes
Packages
Printed circuit boards
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Posed To Me at
Platform & JEDEX
Why will DDR-I at 400 MHz data rate be a
“boutique” solution?
Why will DDR-II at 400 MHz data rate be a
“mainstream” solution?
The answer is to look at what new is going
into DDR-II
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From DDR-I to DDR-II
Lower
Voltage
Prefetch 4
On-Die
Termination
Differential
Strobe
FBGA
Package
Command
Bus
6
The DDR II Family

DDR II similarities to DDR I:


Compatible RAS/CAS command set & protocol
DDR II differences from DDR I:




DDR I = 2.5V, DDR II = 1.8V
Prefetch 4
Differential data strobes
Improved command bus utilization:



Write latency as a function of read latency
Additive latency to help fill holes
New FBGA package & memory modules

Tighter package parasitics
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From DDR-I to DDR-II
Lower
Lower
Voltage
Voltage
Prefetch 4
On-Die
Termination
Differential
Strobe
FBGA
Package
Command
Bus
8
1.8V Signaling
2.5V
VDDQ
VIHac
VIHdc
VREF
VILdc
VILac
1.60V
1.43V
VDDQ
1.25V
1.07V
0.90V
VIHac
VIHdc
VILdc
VILac
VSS
VSS
DDR-I
(SSTL_2)
DDR-II
(SSTL_18)
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1.8V
VREF
1.15V
1.03V
0.90V
0.77V
0.65V
0V
I/O Voltage Impact on Timing
 Signal
integrity is a serious
challenge at high data rates!!! (duh!)
 Assume 1mV/ps edge slew rate
DDR-I = 700 mV (VILVIH) = 700 ps
 DDR-II = 500 mV (VILVIH) = 500 ps

 Helps
meet the need for speed
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1.8V Signaling =
Major Power Savings
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8
7
6
5
4
3
2
1
0
DDR533 @ 1.8V
DDR266 @ 2.5V
PC133 @ 3.3V
Power Efficiency in MB/s per Watt
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From DDR-I to DDR-II
Lower
Voltage
Prefetch 4 4
Prefetch
On-Die
Termination
Differential
Strobe
FBGA
Package
Command
Bus
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Prefetch

Today’s SDRAM architectures assume an
inexpensive DRAM core timing

DDR I (DDR200, DDR266, and DDR333)
prefetches 2 data bits: increase
performance without increasing core
timing costs

DDR II (DDR400, DDR533, DDR667)
prefetches 4 bits internally, but keeps DDR
double pumped I/O
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Prefetch 2 Versus 4
CK
READ
data
Prefetch 2
Core access
time
Prefetch 4
Costs $$$
Essentially free
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Prefetch Impact on Cost
By doubling the prefetch depth, cycle time for column
reads & writes relaxed, improving DRAM yields
DDR
Family
DDR-I
DDR-II
Prefetch
Data
Rate
Cycle
Time
2
266
7.5 ns
2
333
6 ns
2
400
5 ns
4
400
10 ns
4
533
7.5 ns
4
667
6 ns
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Starts to get REAL
EXPENSIVE!
Comparable to
DDR266 in cost
DDR-I 400 Prefetch
 DDR-I
prefetch of 2 means expensive
core timing
 Lower yields
 Conclusion:
DDR-I 400 will maintain
a price premium for a long while
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Why Not Prefetch = 8?
DIMM width = 64 bits
 PCs use 64b, servers use 128b (2
DIMMs)

 64
byte prefetch okay for PC, but…
 128 byte prefetch for servers wastes
bandwidth

DDR-II must service all applications
well to insure maximum volume 
minimum cost
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From DDR-I to DDR-II
Lower
Voltage
Prefetch 4
Differential
Differential
Strobe
Strobe
On-Die
Termination
FBGA
Package
Command
Bus
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Differential Data Strobe

Just as DDR added differential clock to SDR
 DDR II adds differential data strobe to DDR I

Transition at the crosspoint of DQS and DQS

Route these signals as a differential pair


Common mode noise rejection
Matched flight times
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Differential Data Strobe
VREF
DQS
DQS
high time
Normal
balanced
signal
DQS
low time
VREF
DQS
Mismatched
Rise & Fall
signal
Error!
DQS
high
time
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DQS
low time
Differential Data Strobe
DQS
DQS
Normal
balanced
signal
VREF
DQS
high time
DQS
low time
DQS
VREF
DQS
Mismatched
Rise & Fall
signal
DQS
high time
DQS
low time
Significantly reduced symmetry error
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From DDR-I to DDR-II
Lower
Voltage
Prefetch 4
On-Die
Termination
Differential
Strobe
Command
Command
Bus
Bus
FBGA
Package
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Additive Latency
 Command
slot availability is
disrupted by CAS latency even on
seamless read bursts
Sometimes with odd CAS latencies,
sometimes with even
 These collisions can be avoided by
shifting READs and WRITEs in the
command stream

 Additive
latency shifts R & W
commands earlier – applies to both
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Read Latency
 In
the past, data access from a READ
command was simply CAS Latency
 Combined
with Additive Latency,
ability to order commands better
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Read & Additive Latencies
CK
ACT
RD
data
CAS Latency
CK
ACT
RD
RL = AL + CL
data
Additive Latency
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CAS Latency
Write Latency

Complex controllers had collisions
between command slots and data bus
availability

These are eliminated in DDR II by setting
Write Latency = Read Latency – 1

Combined with Additive Latency, lots of
flexibility in ordering commands
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Write & Additive Latencies
CK
ACT
WR
data
Additive Latency = 0
WL = RL – 1
CK
ACT
WR
WL = AL + CL – 1 = RL – 1
Additive Latency
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CL – 1
data
From DDR-I to DDR-II
Lower
Voltage
Prefetch 4
On-Die
Termination
Differential
Strobe
FBGA
FBGA
Package
Package
Command
Bus
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Managing Power
(and its relationship to
packaging)
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Power = CV2f%#
Keys to low
power design:
Factors:
 Capacitance (C)
 Voltage (V)
 Frequency (f)
 Duty cycle (%)
 Power states
(# circuits in use)
Reduce C and V
Match f to demand
Minimize duty cycle
Utilize power states
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Package Capacitance (pF)
TSOP-II Package
Min
Max
Delta
Input Capacitance
2.0
3.0
0.25
Input/Output Capacitance
4.0
5.0
0.50
FBGA Package
Approximate 10-25% reduction
Input Capacitance
1.5
2.5
0.25
Input/Output Capacitance
3.5
4.5
0.50
 Reduced
capacitance lowers power,
makes design easier
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From DDR-I to DDR-II
Lower
Voltage
Prefetch 4
On-Die
On-Die
Termination
Termination
Differential
Strobe
FBGA
Package
Command
Bus
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On-Die Termination
VTT =
VDDQ  2
Data
Controller
DRAM
DDR-I
DRAM
DDR-II
Data
Controller
VDDQ  2
VDDQ  2
Reduces system cost while improving signal
integrity
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DDR-I 400 Issues
DDR-I 400 systems are hard to
design robustly
 No vendor interoperability
guarantees
 DDR-II offers other performance
benefits besides peak data rate
 DDR-I 400 runs hot
 Exists because DDR-II is late

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DDR-I 400 Conclusion

The JEDEC roadmap represents the
industry focus for mainstream
products
 DDR-I
tops out at 333 MHz data rate
 DDR-II starts at 400 MHz data rate
This DOES NOT mean that DDR-I at
400 MHz data rate will not ship in
volume
 It DOES mean that there will be price
premiums for this speed bin

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Modules
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Modules







DDR-I
Unbuffered DIMM
Registered DIMM
SO-DIMM
Micro-DIMM





New:

DDR-II
32b-DIMM
New:

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Unbuffered DIMM
Registered DIMM
SO-DIMM
Micro-DIMM
Mini-DIMM
Unbuffered & Registered
DIMMs
 Same
physical size: 133 mm (5.25”)
 New socket; more pins, tighter pitch
 “Same plane referencing” pinout
 Target markets unchanged
Servers
 Workstations
 Full form factor desktop PC

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SO-DIMM
 Same
size as before: 67.6 x 31.75 mm
 Same 200 pin socket as before

Uses 1.8V key position
 No
longer supports x72 (ECC) or
registered
 Target markets change:
DDR-I: Mobile, blade server
 DDR-II: Does not support blade server,
small form factor PC possible

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Mini-DIMM
to DDR-II… no DDR-I equivalent
 Supports x72 (ECC) and registered
 Larger than SO-DIMM: 82 mm
 New socket required
 Target market: blade server
 Intent is to support stacking
 New

If anyone figures out how to stack BGA
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Micro-DIMM
 Same
footprint: 45.5 x 30-ish mm
 New connector
High pin count mezzanine connector
 Two part: one on mobo, one on module
 0.4 mm pitch

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32b-DIMM
to DDR-I… no DDR-II version yet
 X32 only
 Ultra low cost
 New connector
 Target market: peripherals,
e.g. printers
 New
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What Can Change?
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Small Form Factor PC
 PC
memory usage flattened out
 SO-DIMM or Mini-DIMM meet the
needs of most PCs
 DIMM could yield to smaller module
for most desktop PCs
 Saves ~10,000 mm2 board space
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45
FlexATX Footprint
North Bridge
Copper
Slots
With DIMM:
17k mm2
With SO-DIMM:
Area saved
~ 60%
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7k mm2
Mobile
 DDR-I
SO-DIMM had 2X capacity of
Micro-DIMM (assuming TSOP)
 DDR-II Micro-DIMM has same
capacity as SO-DIMM
 Differences:
SO-DIMM supports 1st generation die
 Micro-DIMM connector change scary

 However,
possible that the MicroDIMM displaces the SO-DIMM for all
mobile market
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Small Module Capacity
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Summary

DDR-II offers many incremental
improvements over DDR-I

Lower voltage, higher prefetch, differential
strobes, more efficient command bus, higher
quality package, on-die termination

DDR-I 400 likely to stay a profitable niche
 New module configurations may impact
markets – watch for growth of MicroDIMM, possible shrink of SO-DIMM in
DDR-II generation
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Thank You
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