Transcript DDR SDRAM Memory Interface Agenda • Why DDR? • DDR vs. SDR • Understanding DDR SDRAM – Bus timing • CoolRunner-II and DDR SDRAM demo board •

DDR SDRAM
Memory Interface
Agenda
• Why DDR?
• DDR vs. SDR
• Understanding DDR SDRAM
– Bus timing
• CoolRunner-II and DDR SDRAM demo board
• CoolRunner-II DDR SDRAM design
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Why DDR?
• DDR = Double Data Rate
• Provides ability to read or write two pieces of information
in each clock cycle
• Doubles the bandwidth of the device without increasing
the clock speed or bus width
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DDR vs. SDR Functionality
• Memory core of DDR and SDR are the same
–
–
–
–
Addressing scheme
Command control interface
Memory bank array structure
Refresh requirements
• The main difference is in the data interface:
– SDR is fully synchronous (posedge of clk)
– DDR is true source-synchronous meaning data is captured
twice per clock cycle, with a bi-directional data strobe (DQS)
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Strobe-Based Data Bus
• To allow for higher data rates, data strobe signals
were added to DDR devices:
– DDR data strobes (DQS) are non-free-running signals
that are driven by the device which is driving the data
signals
• Controller drives DQS for WRITE operations
• DDR SDRAM drives DQS for READ operations
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DDR Enhancements
• DDR utilizes a differential pair for the system clock
(CLK and CLK#)
• Data is transmitted on both positive and negative edges of the clock
• DDR devices incorporate an on-chip delay locked loop (DLL)
• Data strobes are added to improve data capture reliability
• SSTL_2 signaling techniques are used
• DDR utilizes a 2n-prefetch architecture
– Internal data bus is twice the size of external data bus
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SDR vs. DDR Summary
Parameter
DQM
DM (Data Mask)
DQS (Data Strobe)
CK# (System Clock)
Vref
VDD and VDDQ
Signal Interface
Data Rate
Architecture
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SDR
Yes
No
No
No
No
3.3V
LVTTL
1x Clock
Synchronous
DDR
No
Yes
Yes
Yes
Yes
2.5V
SSTL_2
2x Clock
SourceSynchronous
CoolRunner-II DDR SDRAM
Evaluation Board
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CR-II / DDR Demo Board
VTT & VREF Generation
2.5V/1.8V Regulator
LP3964
LP3964
2.5 V
1.8 V
Micro Linear
ML6554
Bus Terminator
VREF Out
VTT Out
CR-II & DDR SDRAM
Xilinx
CR-II
XC2C256
CLK
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Micron
128 Mb DDR
MT46V16M8
SSTL_2 Termination
VTT
VTT
RT
RT
RS
RS
ZO = 50 Ohm
VREF
+
-
VTT
RT
RS
ZO = 50 Ohm
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VREF
+
-
CR-II / DDR Termination
VTT
VTT
ZO = 50 Ohm
VTT
ZO = 50 Ohm
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VREF
128 Mb
DDR SDRAM
CPLD Design
• DDR SDRAM controller design fits into a XC2C256
(~50% utilization for DDR)
• Includes the following:
–
–
–
–
–
Initialization state machine
DDR controller
Refresh logic
Test read/write logic (LFSR)
Board interface
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CPLD Block Diagram
8-bit
LFSR
Refresh Logic
ddr_a
2
ddr_ba
8
rfsh_flag
int_cmd
Initialization / Test Logic
State
Machine
12
int_data
int_addr
DDR
Controller
State Machine
ddr_dq
ddr_dqs
ddr_cke
ddr_cs
ddr_ras
ddr_cas
ddr_we
ddr_clk
Board Logic
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ddr_clkn
DDR Commands
NOP
LOAD MODE REGISTER
Deselect DDR SDRAM. No new commands
executed.
Defines operating mode of SDRAM.
ACTIVE
Opens row in specified bank for access.
READ
Initiates burst read operation.
WRITE
Initiates burst write operation.
BURST TERMINATE
Terminates a burst read.
PRECHARGE
Deactivates open row in specified bank.
AUTO REFRESH
Retains data in SDRAM.
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SDRAM Addressing
Bank
Address
Row Address
Column Address
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Load Mode Register Data
• 23-bit system address bus = 128 MB memory
• SDRAM data is organized into banks
• Each bit location is specified with a row and column address
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Initialization Sequence
Wait for stable power
& clock inputs
Wait 200
Clock Cycles
NOP
Precharge All
Addresses
Precharge All
Addresses
Extended Mode Register
Write (Enable DLL)
Mode Register Write
(Reset DLL)
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Execute 2 Auto
Refresh Commands
Mode Register Write
(Set CAS & burst)
Controller State Machine
cmd = AUTO_REFRESH
cmd = PRECHARGE
PRECHARGE
AUTO_RFS
IDLE
cmd = READ
or WRITE
cmd = LOAD MR
LOAD_MR
ACTIVE
WRITE
READ
BRST_TERM
cnt < CAS_LAT
CAS_LAT
WR_DATA
cmd =
BURST_TERM
RD_DATA
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cnt < BURST_LEN
cnt < BURST_LEN
DDR Clock Requirements
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DDR Clock Generation
Vcc
T
ddr_clk
Q
sys_clk
OBUF
3.3V IN
GCK
2.5V OUT
RST
Vcc
T
sys_clk
OBUF
3.3V IN
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ddr_clkn
Q
GCK
PRE
2.5V OUT
DDR Clock Timing
T = 7.5 ns
sys_clk
tCO = 5 ns
ddr_clk
ddr_clkn
T = 15 ns
7.5 ns
(133 MHz)
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DDR Clock Period
15 ns
(66.67 MHz)
DDR Clock Generation (TCO)
sys_clk
ddr_clk
ddr_clkn
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DDR Clock Generation (VMP)
sys_clk
ddr_clk
ddr_clkn
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Bank/Row Activation
• Prior to a READ/WRITE operation
the specific bank/row must be
activated
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Typical Write Burst
• DQS generated by CPLD
• DQS must be center aligned with DQ
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Typical Read Burst
• DQS is edge aligned to DQ
• Read interrupted with BURST TERMINATE command
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Data Valid Read Window
sys_clk
ddr_clk
ddr_clkn
ddr_dq
D0
D1
DVW
DVW
ddr_dqs
CPLD captures data
DVW = tCK/2 - tAC(max) + tAC(min) = 7.5 ns - (0.75 ns) + (-0.75 ns) = 6 ns
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Data Valid Window
ddr_dqs
ddr_dq(0)
ddr_dq(1)
ddr_dq(2)
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Read & Write (Burst 2)
ddr_clk
ddr_dqs
ddr_dq(0)
ddr_dq(1)
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Read & Write (Burst 4)
ddr_clkn
ddr_clk
ddr_dqs
ddr_dq(0)
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Read & Write (Burst 8)
ddr_clkn
ddr_clk
ddr_dqs
ddr_dq(0)
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Precharge Operation
• Precharge deactivates the open row
in a particular bank or all banks
• After a precharge, the specific row
address must be activated with an
ACTIVE command prior to use
• Auto PRECHARGE : A10 specifies
precharge after current READ/WRITE
operation
• Self PRECHARGE: separate
command (must wait tRP)
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Refresh Requirements
• Refresh is required at intervals of 15.625 µs
– Only one refresh command is required
• Option to issue up to 8 refresh commands every 140.6 µs
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DDR SDRAM Vendors
• Memory vendors providing DDR SDRAM:
– Micron, Infineon, Cypress, Samsung, Hitachi, Fujitsu, Hyundai,
IDT, Mitsubishi, SiberCore, Toshiba...
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Conclusion
• Reference board works up to 100 MHz on DDR SDRAM
• Current DDR design can be modified for SDR SDRAM
applications
• Check out application note XAPP384 on DDR &
CoolRunner-II reference design
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Demo Slides
Demo
Test Control Logic
Burst = 2
8-bit LFSR
8
8
int_data[15:0]
Upper Byte
Lower Byte
DDR Control Logic
ddr_dq[7:0]
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Demo
Data wrote to DDR
MSB … LSB
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Data read from DDR
MSB … LSB
Appendix
SDRAM Core
DQM (SDR only)
Internal Data Bus
Col0 (DDR only)
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SDR Interface
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DDR Interface
Col0
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SSTL_2 Signaling
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DDR Write Logic
8-bit LFSR
lfsr_clk
(TEST SM
Logic)
D
Q
int_data
(TEST SM Logic)
T
ddr_dq[7:0]
Q
ddr_clk
DualEdge
DDR SM Logic
D
Q
ddr_clk
ddr_dqs_t
T
Q
ddr_clk
DualEdge
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ddr_write_en
ddr_dqs
DDR Read Logic
DDR SM Logic
T
Q
ddr_read_en
ddr_clk
DualEdge
ddr_dq[7:0]
ddr_dqs
D
CE
Q
int_data_rd[15:8]
sys_clk
ddr_dqs
ddr_dq[7:0]
D
sys_clk
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CE
Q
int_data_rd[7:0]
LED
Board
Logic
CLK/CLK# Generation
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