No Slide Title

Download Report

Transcript No Slide Title

Digital Integrated
Circuits
A Design Perspective
The Devices
July 30, 2002
© Digital Integrated Circuits2nd
Devices
What is a Transistor?
A Switch!
An MOS Transistor
VGS  V T
|VGS|
Ron
S
© Digital Integrated Circuits2nd
D
Devices
The MOS Transistor
Polysilicon
© Digital Integrated Circuits2nd
Aluminum
Devices
MOS Transistors Types and Symbols
D
D
G
G
S
S
NMOS Enhancement NMOS Depletion
D
G
G
S
PMOS Enhancement
© Digital Integrated Circuits2nd
D
B
S
NMOS with
Bulk Contact
Devices
Threshold Voltage: Concept
+
S
VGS
-
D
G
n+
n+
Depletion
Region
n-channel
p-substrate
B
© Digital Integrated Circuits2nd
Devices
The Threshold Voltage
© Digital Integrated Circuits2nd
Devices
The Body Effect
0.9
0.85
0.8
0.75
VT (V)
0.7
0.65
0.6
0.55
0.5
0.45
0.4
-2.5
-2
-1.5
-1
V
BS
© Digital Integrated Circuits2nd
-0.5
0
(V)
Devices
Current-Voltage Relations
A good ol’ transistor
6
x 10
-4
VGS= 2.5 V
5
Resistive
Saturation
4
ID (A)
VGS= 2.0 V
3
VDS = VGS - VT
2
VGS= 1.5 V
1
0
Quadratic
Relationship
VGS= 1.0 V
0
0.5
1
1.5
2
2.5
VDS (V)
© Digital Integrated Circuits2nd
Devices
Transistor in Linear
VGS
VDS
S
G
n+
–
V(x)
ID
D
n+
+
L
x
p-substrate
B
MOS transistor and its bias conditions
© Digital Integrated Circuits2nd
Devices
Transistor in Saturation
VGS
VDS > VGS - VT
G
D
S
n+
-
VGS - VT
+
n+
Pinch-off
© Digital Integrated Circuits2nd
Devices
Current-Voltage Relations
Long-Channel Device
© Digital Integrated Circuits2nd
Devices
u n (m/s)
Velocity Saturation
usat = 105
Constant velocity
Constant mobility (slope = µ)
xc = 1.5
© Digital Integrated Circuits2nd
x (V/µm)
Devices
Perspective
ID
Long-channel device
VGS = VDD
Short-channel device
V DSAT
© Digital Integrated Circuits2nd
VGS - V T
VDS
Devices
ID versus VGS
-4
6
x 10
-4
x 10
2.5
5
2
4
linear
quadratic
ID (A)
ID (A)
1.5
3
1
2
0.5
1
0
0
quadratic
0.5
1
1.5
VGS(V)
Long Channel
© Digital Integrated Circuits2nd
2
2.5
0
0
0.5
1
1.5
2
2.5
VGS(V)
Short Channel
Devices
ID versus VDS
-4
6
-4
x 10
VGS= 2.5 V
x 10
2.5
VGS= 2.5 V
5
2
Resistive Saturation
ID (A)
VGS= 2.0 V
3
VDS = VGS - VT
2
1
VGS= 1.5 V
0.5
VGS= 1.0 V
VGS= 1.5 V
1
0
0
VGS= 2.0 V
1.5
ID (A)
4
VGS= 1.0 V
0.5
1
1.5
VDS(V)
Long Channel
© Digital Integrated Circuits2nd
2
2.5
0
0
0.5
1
1.5
2
VDS(V)
Short Channel
Devices
2.5
A PMOS Transistor
-4
0
x 10
VGS = -1.0V
-0.2
VGS = -1.5V
ID (A)
-0.4
-0.6
-0.8
-1
-2.5
VGS = -2.0V
Assume all variables
negative!
VGS = -2.5V
-2
-1.5
-1
-0.5
0
VDS (V)
© Digital Integrated Circuits2nd
Devices
Transistor Model
for Manual Analysis
© Digital Integrated Circuits2nd
Devices
The Transistor as a Switch
VGS  V T
Ron
S
ID
V GS = VD D
D
Rmid
R0
V DS
VDD/2
© Digital Integrated Circuits2nd
VDD
Devices
The Transistor as a Switch
7
x 10
5
6
5
Req (Ohm)

4
3

2
1
0
0.5
1
1.5
V
DD
© Digital Integrated Circuits2nd
2
The resistance inversely
proportional to W/L
Once VDD approaches
VT, the resistance
dramatically increases.
2.5
(V)
Devices
The Transistor as a Switch


© Digital Integrated Circuits2nd
Req-p ~ 2.5 Req-n
Electron mobility ~ 2.5 Hole
mobility, depending on supply
voltage and doping concentration
Devices
MOS Capacitances
Gate capacitance
 Diffusion (Junction) capacitance

G
CGS
CGD
D
S
CGB
CSB
CDB
B
© Digital Integrated Circuits2nd
Devices
The Gate Capacitance
Polysilicon gate
Source
n+
Drain
xd
xd
Ld
W
n+
Gate-bulk
overlap
Top view
Gate oxide
tox
n+
L
n+
Cross section
© Digital Integrated Circuits2nd
Devices
Gate Capacitance
G
G
CGC
CGC
D
S
G
Cut-off
CGC
D
S
Resistive
D
S
Saturation
Most important regions in digital design: saturation and cut-off
© Digital Integrated Circuits2nd
Devices
Diffusion Capacitance
Channel-stop implant
N A1
Side wall
Source
ND
W
Bottom
xj
Side wall
LS
© Digital Integrated Circuits2nd
Channel
Substrate N A
Devices
Capacitances in 0.25 mm CMOS
process
© Digital Integrated Circuits2nd
Devices
Summary of MOSFET Operating Regions

Strong Inversion VGS > VT
 Linear (Resistive) VDS < VDSAT
 Saturated (Constant Current) VDS  VDSAT

Weak Inversion (Sub-Threshold) VGS  VT
 Exponential in VGS with linear VDS dependence
I D  I 0e
qVGS
nkT
qV
 DS

1  e kT


© Digital Integrated Circuits2nd




VDS from 0 to 0.5V
Devices
Parasitic Resistances
Polysilicon gate
LD
G
Drain
contact
D
S
RS
W
VGS,eff
RD
Drain
RD = LD/W * R + RC
© Digital Integrated Circuits2nd
Devices
Latch-up
 Tyrister
alike, n-p-n-p
 To prevent,
 minimize Rwell, Rpsubs
 Guard ring
© Digital Integrated Circuits2nd
Devices