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The MOS Transistor
Gate Oxyde
Gate
Source
Polysilicon
n+
Drain
n+
p-substrate
Field-Oxyde
(SiO2)
p+ stopper
Bulk Contact
CROSS-SECTION of NMOS Transistor
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Cross-Section of CMOS
Technology
Digital Integrated Circuits
Devices
© Prentice Hall 1995
MOS transistors
Types and Symbols
D
D
G
G
S
S
NMOS Enhancement NMOS Depletion
D
D
G
G
S
S
PMOS Enhancement
Digital Integrated Circuits
B
Devices
NMOS with
Bulk Contact
© Prentice Hall 1995
Threshold Voltage: Concept
+
S
VGS
-
D
G
n+
n+
n-channel
Depletion
Region
p-substrate
B
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Current-Voltage Relations
VGS
VDS
S
G
n+
–
V(x)
ID
D
n+
+
L
x
p-substrate
B
MOS transistor and its bias conditions
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Current-Voltage Relations
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Transistor in Saturation
VGS
VDS > VGS - VT
G
D
S
n+
Digital Integrated Circuits
-
VGS - VT
Devices
+
n+
© Prentice Hall 1995
I-V Relation
VDS = VGS-VT
Saturation
ID (mA)
VGS = 4V
1
VGS = 3V
VGS = 2V
VGS = 1V
0.0
1.0
2.0
3.0
VDS (V)
4.0
5.0
0.020
÷ID
Triode
Square Dependence
2
VGS = 5V
0.010
Subthreshold
Current
0.0
2.0
VT1.0
VGS (V)
3.0
(b) ID as a function of VGS
(for VDS = 5V).
(a) ID as a function of VD S
NMOS Enhancement Transistor: W = 100 m, L = 20 m
Digital Integrated Circuits
Devices
© Prentice Hall 1995
A model for manual analysis
Digital Integrated Circuits
Devices
© Prentice Hall 1995
The Sub-Micron MOS Transistor
• Threshold Variations
• Parasitic Resistances
• Velocity Sauturation and Mobility Degradation
• Subthreshold Conduction
• Latchup
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Threshold Variations
VT
VT
Long-channel threshold
VDS
L
Threshold as a function of
the length (for low VDS)
Digital Integrated Circuits
Low VDS threshold
Drain-induced barrier lowering
(for low L)
Devices
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Parasitic Resistances
Polysilicon gate
LD
G
Drain
contact
W
VGS,eff
D
S
RS
RD
Drain
Digital Integrated Circuits
Devices
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Velocity Saturation (1)
constant velocity
Constant mobility (slope = )
Esat
E V/m)
700
250
0
EtV/m)
(b) Mobility degradation
(a) Velocity saturation
Digital Integrated Circuits
n0
7
2
n (cm /Vs)
n (cm/sec)
sat = 10
Devices
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Velocity Saturation (2)
1.5
0.5
VGS = 3
0.5
VGS = 2
VGS = 1
0.0
1.0
2.0
VDS
3.0
(V)
4.0
5.0
(a) I D as a function of VDS
ID (mA)
VGS = 4
I D (mA)
1.0
Linea r Dependence
VGS = 5
0
0.0
1.0
2.0
VGS (V)
3.0
(b) ID as a function of VGS
(for VDS = 5 V).
Linear Dependence on VGS
Digital Integrated Circuits
Devices
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Sub-Threshold Conduction
102
ln(ID) (A)
104
Linear region
106
108
1010
10120.0
Digital Integrated Circuits
Subthreshold exponential region
VT 1.0
2.0
3.0
VGS (V)
Devices
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Latchup
VD D
VDD
+
p
+
n
n+
+
p
+
n+
p
n-well
p-source
Rnwell
Rpsubs
n-source
p-substrate
(a) Origin of latchup
Digital Integrated Circuits
Rnwell
Devices
Rpsubs
(b) Equivalent circuit
© Prentice Hall 1995
SPICE MODELS
Level 1: Long Channel Equations - Very Simple
Level 2: Physical Model - Includes Velocity
Saturation and Threshold Variations
Level 3: Semi-Emperical - Based on curve fitting
to measured devices
Level 4 (BSIM): Emperical - Simple and Popular
Digital Integrated Circuits
Devices
© Prentice Hall 1995
MAIN MOS SPICE PARAMETERS
Digital Integrated Circuits
Devices
© Prentice Hall 1995
SPICE Transistors Parameters
Digital Integrated Circuits
Devices
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SPICE Parameters for Parasitics
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Technology Evolution
Digital Integrated Circuits
Devices
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The CMOS Inverter:
A First Glance
VDD
Vin
Vout
CL
Digital Integrated Circuits
Devices
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VTC of Real Inverter
5.0
Vout (V)
4.0
NML
3.0
2.0
VM
NMH
1.0
0.0
Digital Integrated Circuits
1.0
2.0
3.0
Vin (V)
Devices
4.0
5.0
© Prentice Hall 1995
Dynamic Behavior of MOS Transistor
G
CGS
CGD
D
S
CGB
CSB
CDB
B
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Delay Definitions
VDD
VDD
Vin
M2
50%
Vin
Cg4
Cdb2
Cgd12
M4
Vout
Vout2
t
Vout
t
pHL
Cdb1
t
pLH
Cw
M1
Cg3
M3
Interconnect
90%
Fanout
50%
10%
tf
Digital Integrated Circuits
t
tr
Simplified
Model
Devices
Vin
Vout
CL
© Prentice Hall 1995
CMOS Inverters
VDD
PMOS
1.2m
=2l
Out
In
Metal1
Polysilicon
NMOS
GND
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Using Cascaded Buffers
In
Out
Ci
u2
u
1
C1
u N-1
C2
CL
uopt = e
Digital Integrated Circuits
Devices
© Prentice Hall 1995
COMBINATIONAL
LOGIC
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Static CMOS
VDD
In1
In2
In3
PUN
PMOS Only
F=G
In1
In2
In3
PDN
NMOS Only
VSS
PUN and PDN are Dual Networks
Digital Integrated Circuits
Devices
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Example Gate: NAND
Digital Integrated Circuits
Devices
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4-input NAND Gate
Vdd
VDD
VDD
In1
In2
In3
In4
Out
In1
In2
Out
In3
Out
In4
GND
In1 In2 In3 In4
GND
In1 In2 In3 In4
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Where Does Power Go in CMOS?
• Dynamic Power Consumption
Charging and Discharging Capacitors
• Short Circuit Currents
Short Circuit Path between Supply Rails during Switching
• Leakage
Leaking diodes and transistors
Digital Integrated Circuits
Devices
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SEQUENTIAL LOGIC
Digital Integrated Circuits
Devices
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Master-Slave Flip-Flop
SLAVE
MASTER
J
S
Q
K
R
Q
SI
RI
S
Q
Q
R
Q
Q
PRESET
J
K
Q
Q
CLEAR
Digital Integrated Circuits
Devices
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The Ellmore Delay
Digital Integrated Circuits
Devices
© Prentice Hall 1995
The Clock Skew Problem
Clock Rates as High as 500 Mhz in CMOS!
t’
In
CL1
R1
ti
t’’
CL2
R2
t ’’’
CL3
R3
Out
tl,min t r,min
tl,max t r,max
Clock Edge Timing Depends upon Position
Digital Integrated Circuits
Devices
© Prentice Hall 1995