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VLSI Devices
Intuitive understanding of device
operation
 Fundamental analytic models

 Manual Models
 Spice Models
Secondary and deep-sub-micron effects
 Junction Diode and FET
 Resistor and Capacitor

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Devices
The Diode
B
A
Al
SiO2
p
n
Cross-section of pn-junction in an IC process
A
p
Al
A
n
B
One-dimensional
representation
B
diode symbol
Occurs as parasitic element in Digital ICs
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Depletion Region
hole diffusion
electron diffusion
(a) Current flow.
n
p
hole drift
electron drift
Charge
Density

x
Distance
+
-
Electrical
Field
(b) Charge density.

x
(c) Electric field.
V
Potential
-W 1
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
W2
x
(d) Electrostatic
potential.
Devices
pn (W2)
Forward Bias
pn0
Lp
np0
p-region
-W1 0
W2
n-region
x
diffusion
Forward Bias usually avoided in Digital ICs
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Reverse Bias
pn0
np0
p-region
-W1 0
W2
x
n-region
diffusion
Diode Isolation Mode
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Diode Current
I D  I s (e
VD / kT
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1)
Devices
Models for Manual Analysis
+
IIDD =ISI(es (VeDV/DT/ kT– 1)1)
VD
ID
+
+
VD
–
(a) Ideal diode model
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–
VDon
–
(b) First-order diode model
Devices
Junction Capacitance
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Devices
Diffusion Capacitance (Forward Bias)
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Secondary Effects
ID (A)
0.1
0
–0.1
–25.0
–15.0
–5.0
0
5.0
VD (V)
Avalanche Breakdown
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Diode Model (Manual Analysis)
RS
+
VD
ID
CD
-
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SPICE Parameters

Transit time models charge storage
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Devices
What is a Transistor?

A Switch!


VGS  V T

Ron
S
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D

Resistor is poor model in
saturation– current source
Source and Drain are symmetric
N-channel: Source is most
negative of the two
P-channel: Source is most
positive of the two
Four Modes:




Off (leakage current only)
Sub-Threshold (exponential)
Linear (Resistive)
Saturation (Current Source)
Devices
The MOS Transistor
Polysilicon
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Aluminum
Devices
MOS Transistors Types and Symbols
D
D
G
G
S
S
NMOS Enhancement NMOS Depletion
D
G
G
S
PMOS Enhancement
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D
B
S
NMOS with
Bulk Contact
Devices
Threshold Voltage: Concept
+
S
VGS
-
D
G
n+
n+
Depletion
Region
n-channel
p-substrate
B
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Devices
The Threshold Voltage
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The Body Effect
0.9
0.85
0.8
0.75
VT (V)
0.7
0.65
0.6
0.55
0.5
0.45
0.4
-2.5
-2
-1.5
-1
V
BS
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-0.5
0
(V)
Devices
Current-Voltage Relation
6
x 10
-4
VGS= 2.5 V
5
Resistive
Saturation
4
ID (A)
VGS= 2.0 V
3
VDS = VGS - VT
2
VGS= 1.5 V
1
0
Quadratic
Relationship
VGS= 1.0 V
0
0.5
1
1.5
2
2.5
VDS (V)
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Devices
Transistor in Linear
VGS
VDS
S
G
n+
–
V(x)
ID
D
n+
+
L
x
p-substrate
B
MOS transistor and its bias conditions
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Devices
Transistor in Saturation
VGS
VDS > VGS - VT
G
D
S
n+
-
VGS - VT
+
n+
Pinch-off
Region
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Devices
Current-Voltage Relations
Long-Channel Device
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Devices
A model for manual analysis
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Devices
Current-Voltage Relations:
Deep-Submicron FET
2.5
x 10
-4
VGS= 2.5 V
Early Saturation
2
VGS= 2.0 V
ID (A)
1.5
VGS= 1.5 V
1
0.5
0
Linear
Relationship
VGS= 1.0 V
0
0.5
1
1.5
2
2.5
VDS (V)
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Devices
u n (m/s)
Velocity Saturation
usat = 105
Constant velocity
Constant mobility (slope = µ)
c = 1.5
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 (V/µm)
Devices
Perspective
ID
Long-channel device
VGS = VDD
Short-channel device
V DSAT
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VGS - V T
VDS
Devices
ID versus VGS
-4
6
x 10
-4
x 10
2.5
5
2
4
linear
quadratic
ID (A)
ID (A)
1.5
3
1
2
0.5
1
0
0
quadratic
0.5
1
1.5
VGS(V)
Long Channel
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2
2.5
0
0
0.5
1
1.5
2
2.5
VGS(V)
Short Channel
Devices
ID versus VDS
-4
6
-4
x 10
VGS= 2.5 V
x 10
2.5
VGS= 2.5 V
5
2
Resistive Saturation
ID (A)
VGS= 2.0 V
3
VDS = VGS - VT
2
1
VGS= 1.5 V
0.5
VGS= 1.0 V
VGS= 1.5 V
1
0
0
VGS= 2.0 V
1.5
ID (A)
4
VGS= 1.0 V
0.5
1
1.5
VDS(V)
Long Channel
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2
2.5
0
0
0.5
1
1.5
2
VDS(V)
Short Channel
Devices
2.5
A unified model
for manual analysis
G
S
D
B
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Devices
Simple Model versus SPICE
2.5
x 10
-4
VDS=VDSAT
2
Velocity
Saturated
ID (A)
1.5
Linear
1
VDSAT=VGT
0.5
VDS=VGT
0
0
0.5
Saturated
1
1.5
2
2.5
VDS (V)
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Devices
A PMOS Transistor
-4
0
x 10
VGS = -1.0V
-0.2
VGS = -1.5V
ID (A)
-0.4
-0.6
-0.8
-1
-2.5
VGS = -2.0V
VGS = -2.5V
-2
-1.5
-1
-0.5
0
VDS (V)
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Transistor Model
for Manual Analysis
0.5 mm
Vt
Gamma
Vd(sat)
k’ (mA/V2)
Lambda
NMOS
0.7-0.8
0.48
3.1
50-60
0.04*
PMOS
-0.91-0.97
0.59
-6.5
-17-20
-0.07*
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The Transistor as a Switch
VGS  V T
Ron
S
ID
V GS = VD D
D
Rmid
R0
V DS
VDD/2
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VDD
Devices
The Transistor as a Switch
7
x 10
5
6
Req (Ohm)
5
4
3
2
1
0
0.5
1
1.5
V
DD
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2
2.5
(V)
Devices
The Transistor as a Switch
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MOS Capacitances
Dynamic Behavior
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Dynamic Behavior of MOS Transistor
G
CGS
CGD
D
S
CGB
CSB
CDB
B
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The Gate Capacitance
Polysilicon gate
Source
Drain
xd
n+
xd
Ld
W
n+
Gate-bulk
overlap
Top view
Gate oxide
tox
n+
L
n+
Cross section
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Gate Capacitance
G
G
CGC
CGC
D
S
G
Cut-off
CGC
D
S
Resistive
D
S
Saturation
Most important regions in digital design: saturation and cut-off
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Gate Capacitance
CG C
WLC ox
WLC ox
2
CGC B
C G CS = CG CD
CG C
Capacitance as a function of VGS
(with VDS = 0)
2WLC ox
CG CS
3
WLC ox
CGCD
2
VG S
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WLC ox
0
VDS /(VG S-VT)
1
Capacitance as a function of the
degree of saturation
Devices
Diffusion Capacitance
Channel-stop implant
N A1
Side wall
Source
ND
W
Bottom
xj
Side wall
LS
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Channel
Substrate N A
Devices
Junction Capacitance
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Linearizing the Junction Capacitance
Replace non-linear capacitance by
large-signal equivalent linear capacitance
which displaces equal charge
over voltage swing of interest
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MOS Capacitances in 0.25/0.5 mm
CMOS processes
0.5um
AMI/C5
Cox
fF/mm2
C0
fF/mm
Cj
fF/mm2
mj
b
V
Cjsw
fF/mm
mjsw
bsw
V
NMOS
2.5
0.20
0.44
0.34
0.90
0.28
0.35
0.89
PMOS
2.4
0.28
0.73
0.5
0.91
0.33
0.32
0.90
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The Sub-Micron MOS Transistor
 Threshold
Variations
 Subthreshold Conduction
 Parasitic Resistances
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Threshold Variations
VT
VT
Long-channel threshold
L
Threshold as a function of
the length (for low VDS )
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Low VDS threshold
VDS
Drain-induced barrier lowering
(for low L)
Devices
Sub-Threshold Conduction
The Slope Factor
-2
10
Linear
-4
I D ~ I 0e
10
-6
Quadratic
CD
, n  1
Cox
S is DVGS for ID2/ID1 =10
ID (A)
10
qVGS
nkT
-8
10
-10
Exponential
-12
VT
10
10
0
0.5
1
1.5
2
2.5
Typical values for S:
60 .. 100 mV/decade
VGS (V)
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Sub-Threshold ID vs VGS
I D  I 0e
qVGS
nkT
qV
 DS

1  e kT






VDS from 0 to 0.5V
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Sub-Threshold ID vs VDS
I D  I 0e
qVGS
nkT
qV
 DS

1  e kT



1    VDS 


VGS from 0 to 0.3V
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Summary of MOSFET Operating
Regions
 Strong
Inversion VGS > VT
 Linear (Resistive) VDS < VDSAT
 Saturated (Constant Current) VDS  VDSAT
 Weak
Inversion (Sub-Threshold) VGS  VT
 Exponential in VGS with linear VDS dependence
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Parasitic Resistances
Polysilicon gate
LD
G
Drain
contact
D
S
RS
W
VGS,eff
RD
Drain
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Latch-up
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Future Perspectives
25 nm FINFET MOS transistor
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Problems HW3
1.
2.
3.
Rabaey Chap. 3 on-line problems: 2, 3(do not do the spice simulation), 6,
9(L=0.5um)
Consider an inverter built with 1/0.5 (nmos W/L) and 2/0.5 (pmos) transistors.
Draw a sue schematic for the inverter driving a 10fF load capacitor (other
terminal is grounded). Using your model for the AMI FET transistors,
determine the peak current flowing into the FET after both an abrupt rising
and falling edge on the inverter input, given a supply voltage of 3.3 Volts and
using the Mosis extracted parameters from the MOSIS or the class website.
Simulate these transitions using spice from the Sue schematic.
Complete the Max layout of the full adder cells and build a schematic in sue
for each cell and for an 8-bit ripple carry adder. Be sure to use the same
transistor sizes in the schematic as you had in your layout. Simulate the
adder for the following transition: a=0->1, b=255 Plot the sum and carry
outputs and estimate the total carry chain delay and delay per stage.
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