Transcript Slide 1
MOS Field-Effect Transistors for High-Speed Operation D.L. Pulfrey Department of Electrical and Computer Engineering University of British Columbia Vancouver, B.C. V6T1Z4, Canada [email protected] http://nano.ece.ubc.ca Day 4A, May 30, 2008, Pisa Si MOSFET features • 4 terminals • 2D-device • "The most abundant object made by mankind" NP-junctions and transistor action HBT, BJT B MOSFET G Cox RB E C Rj S x=0 x=0 Vaj V BE Cs=dQs/dVaj Rj Vaj VGS RB R j 1 1 C s (VGS ) / C ox if C s (VGS ) C ox V BE Vaj VGS Q (0) exp(qVBE / kT ) Q(0) exp(qVGS / kT ) and and I D exp(qVGS / kT ) I C exp(qVBE / kT ) What happens if C s (VGS ) C ox ? D Transistor transfer characteristics BJT: MOSFET: E/B: 1E19/1E17 S/B: 1E20/8E17 Vbi ON Getting HOT Note: relative "linearities" and current ranges "OFF" Sub-threshold ON SUB-THRESHOLD CONDITION (DEPLETION) - + + + + - - - - - - - - VSB • Depletion layer forms iG VGS + VDS + - iB - - + + x y iG QG t iB QB t CGG QG VG C BG QB VG ON CONDITION (Strong Inversion) - VGS + • Inversion layer forms VDS + iG + + + + + + + + + iD iS - - - - - - - VSB - iB QG iG t QnS iS t x y C SG QB iB t QnD iD t Q nS V G Decomposing the MOSFET 1. Ignore S and D 2. Take vertical section from G → B x y EC Note: • n+ poly gate • work functions • oxide electron affinity and Eg y Equilibrating the MOSCAP - electrons transfer, driven by difference in EF Equilibration - electrons recombine in body at the interface process: - depletion layer forms - charge separation creates field in oxide = -Vfb Surface potential and the PSP model qB Introducing the channel potential THE GRADUAL CHANNEL APPROXIMATION Implicit expression for s Varying degrees of inversion along the channel The Drain Current Charge Sheet Approximation & Depletion Approximation DDE IEEE convention Drain I-V characteristics • Diffusion in sub-threshold • Drift in strongly ON • Smooth curves ! Saturation and loss of inversion In Saturation: • Qn(L) becomes very small. • Field lines from gate terminate on acceptors in body. • Drain end of channel is NOT in strong inversion, • but SPICE models assume that it is ! Development of SPICE Level 1 model From PSP: Make stronginversion assumptions Use Binomial Expansion Threshold voltage Comparison of PSP and SPICE VDS (V) Improving the SPICE model • Increase s at strong inversion SPICE Level 49: allowing for vsat v =E(x) Combining the velocities: v=vsat v( x) 1 1 1 ( x) v sat Putting this together with : GCA, CSM, dVCS(x)/dx Comparison of SPICE Levels 1 and 49 Subthreshold current From PSP: Weak inversion: Expand Qn and substitute in PSP Diffusion Equation. Convert s to VGS: Subthreshold current: Subthreshold current comparison Si CMOS: why is it dominant for digital? 4 reasons: IN OUT VSS VDD pFET nFET Example of small footprint 1. "Low" OFF current. 2. Compact logic: few transistors and no level shifting. 3. Small footprint. 4. Industrial investment. CMOS: the Industrial drive Nodes relate to the DRAM half pitch, i.e., the width, and space in between, metal lines connecting DRAM bit cells Logic speed is about Q and I Need: • high - certainly • Low L - but it adversely affects VT • High Cox - but low CoxZL • Low VDD - but it adversely affects ION • Low VT - but it adversely affects ISUBT 3 major concerns for digital CMOS 1. Increasing ION via mobility improvement 2. Reducing gate leakage via thicker, high-k dielectrics 3. Controlling VT and Isubt via suppression of the short-channel effect Improving : direction-dependent m* • k1 is a <100> direction • k2 and k3 are orthogonal at the point of the energy minimum EC Which direction has the higher effective mass? Conductivity effective mass mC* Electron accelerates in field E and reaches vd on next collision after time F ma v =0 v =vd m vd q qE vd * E mC q 2 n J E qnE E mC* n 2 4 q * * 6 m/ mt 2 1 1 q 2 n * * mt 3 m/ 2 What happens when Si is biaxially tensioned? For unstrained <100> Si: mC* = 0.26m0 Effect of biaxial tensile strain on EC Unstrained • 4 valleys raised in energy • 2 valleys lowered in energy n 2 4 * * 6 m/ mt 2 1 1 mC* * * mt 3 m/ 1 2 (ideally)t o * 2 mt q 2 Strained Si at the 45nm node High-k dielectrics Cox ox t ox • High COX needed for ID and S • High tOX needed to reduce gate leakage • Resolve conflict by increasing E Simplify the U profile → y (10 nm) Solve SWE in each region: write as: d 2 2 k y0 2 dx Electron energy Tunneling through the oxide Solutions for * Physically what is the "D-wave" ? What is * ? Why is it : -oscillatory in the channel ? - damped in the oxide ? - constant in the gate ? y (m) Transmission Probability: Definition 1. For the channel: 3. Define the Transmission Probability: 2. Do the derivatives and the conjugates: What is the interpretation of this ? What do these mean ? Silica, hafnia, and electron affinity Tunneling current 100% improvement in Cox I tunn (k 4 k silica ) I tunn (k silica ) 50% improvement in Cox (k 4 k silica ) The Short-Channel Effect s = f (L, VDS) VT = f (L, VDS) s is determined by capacitive coupling via Cox and Cbody, AND by capacitive coupling via CDS Reduce CDS by shrinking yj new yj It's like reducing the area of a parallel plate capacitor yj SCE on Drain Current 100/150 ---L/yj (nm/nm) = 100/30 ---50/30 100/"0" ---- Reduce CDS by screening Ex Using SOI to beat SCE Alvin Loke Daryl Van Vorst