Transcript Instruction Fetch, Instruction Field Extraction

How Computers Work
Lecture 5
Memory Implementation
How Computers Work Lecture 5 Page 1
A Top-Down View of the Beta Architecture
With st(ra,C,rc) : Mem[C+<rc>] <- <ra>
PC
Q
XADDR
RA1
Memory
RD1
ISEL
JMP(R31,XADDR,XP)
0
1
31:26
25:21
OPCODE
RA
20:5
9:5
4:0
C
RB
RC
+1
0
OPCODE
RA1
Register File
RD1
ASEL
0
RA2
Register File
RD2
SEXT
1 2
1
1
0
A
BSEL
B
ALU
A op B
ALUFN
Z
RA2
Memory
RD2
PCSEL
0
1
D
PC
0
WD
Memory
WA
WE
1
WD
Register File
WEMEM
2
WDSEL
WA
RC
WE
WERF
How Computers Work Lecture 5 Page 2
Today’s Lecture:
How do we build these?
RA1
Memory
RD1
RA1
Register File
RD1
RA2
Register File
RD2
RA2
Memory
RD2
WD
Memory
WA
WE
WD
Register File
WA
WE
How Computers Work Lecture 5 Page 3
Recall the Enable-Controlled Register
D
Q
32
E
32
CLK
How Computers Work Lecture 5 Page 4
How do we select 1 of 31 registers to read?
D
Q
E
D
Q
E
.
.
.
D
Q
E
How Computers Work Lecture 5 Page 5
A: Add an output selector.
D
Q
E
D
Q
E
RD1 = <RA1>
.
.
.
D
Q
E
0
RA1
How Computers Work Lecture 5 Page 6
Q: How do we add a second port?
D
Q
E
D
Q
E
RD1 = <RA1>
.
.
.
D
Q
E
0
RA1
How Computers Work Lecture 5 Page 7
A: Add a second multiplexor
D
Q
E
D
Q
E
RD1 = <RA1>
.
.
.
RD2 = <RA2>
D
Q
E
0
0
RA1
RA2
How Computers Work Lecture 5 Page 8
Q: How do we write selectively?
D
Q
E
D
Q
E
RD1 = <RA1>
.
.
.
RD2 = <RA2>
D
Q
E
0
0
RA1
RA2
How Computers Work Lecture 5 Page 9
A: Use a decoder on the Enables
WD
D
Q
0
0
E
0
D
Q
1
1
E
1
RD1 = <RA1>
.
.
.
WERF
RD2 = <RA2>
D
Q
30
31
WA
30
E
30
0
31
RA1
0
31
RA2
How Computers Work Lecture 5 Page 10
The Decoder / Demultiplexor
How Computers Work Lecture 5 Page 11
To minimize wires:
WD
WD
D
D
Q
0
0
Q
E
0
D
1
Q
E
1
WA
RD2
D
Q
31
1
.
.
.
D
30
E
RD1
.
.
.
WERF
0
D
Q
1
E
30
E
Q
30
0
31
RA1
31
E
30
0
31
RA2
How Computers Work Lecture 5 Page 12
Q: What about the clocks?
WD
D
Q
0
0
E
0
D
Q
1
1
E
1
RD1 = <RA1>
.
.
.
WERF
RD2 = <RA2>
D
Q
30
31
WA
30
E
30
0
31
RA1
0
31
RA2
How Computers Work Lecture 5 Page 13
A: Connect them all together.
WD
D
Q
0
0
E
0
D
Q
1
1
E
1
RD1 = <RA1>
.
.
.
WERF
RD2 = <RA2>
D
Q
30
E
31
WA
30
30
0
Clock
31
RA1
0
31
RA2
How Computers Work Lecture 5 Page 14
Q: Is it practical to do the big
Memory this way?
A: NO
How Computers Work Lecture 5 Page 15
Minimize per-bit circuitry
.
.
.
...
How Computers Work Lecture 5 Page 16
1 Bit Cell
How Computers Work Lecture 5 Page 17
Minimizing per-bit circuitry
.
.
.
...
Sense Amplifiers
How Computers Work Lecture 5 Page 18
How about ROMs?
How Computers Work Lecture 5 Page 19
Q: What can we use for a switch?
A: The Field-Effect Transistor
How Computers Work Lecture 5 Page 20
The N-Channel FET (NFET)
L
H
How Computers Work Lecture 5 Page 21
The P-Channel FET (PFET)
L
H
How Computers Work Lecture 5 Page 22
How do we implement multiple ports?
• 2 Read and 1 Write Ports
– For now, LD and ST instructions are mutually
exclusive.
• 1 RD + 1 RD/WR port needed
• LD and ST are don’t happen that often
– Most of the time only 1RD port necessary
• Easy answer : Do them sequentially
– Need a way to “stall” machine waiting for Mem
How Computers Work Lecture 5 Page 23
Q: How do we stall this machine?
PC
Q
XADDR
RA1
Memory
RD1
ISEL
JMP(R31,XADDR,XP)
0
1
31:26
25:21
OPCODE
RA
20:5
9:5
4:0
C
RB
RC
+1
0
OPCODE
RA1
Register File
RD1
ASEL
0
RA2
Register File
RD2
SEXT
1 2
1
1
0
A
BSEL
B
ALU
A op B
ALUFN
Z
RA2
Memory
RD2
PCSEL
0
1
D
PC
0
WD
Memory
WA
WE
1
WD
Register File
WEMEM
2
WDSEL
WA
RC
WE
WERF
How Computers Work Lecture 5 Page 24
A: Stalls are done by:
• Disabling WERF
• Disabling Memory Write
• Disabling PC write
How Computers Work Lecture 5 Page 25
Another Approach - Increasing
Memory Bandwidth
• Make memory twice as wide
– 64 Bits Instead of 32
• Should work out in the long run, as 2 words are read per
machine cycle, but
– Words read are next to each other in address space
– Need a place to stash the extra word
– Sometimes, the stashed word isn’t used.
How Computers Work Lecture 5 Page 26
Summary
• What Did we learn today?
– How to Implement Registers + Big Memory
– Multi-Port Big Memories aren’t easy
• Sequential Access (stalls + extra logic)
• Wide Access + Some sort of cache + extra logic
• Recitation
– Review of today’s lecture
How Computers Work Lecture 5 Page 27