Transcript Introduction to Interpretation

How Computers Work
Lecture 6
Finite State Machines
How Computers Work Lecture 6 Page 1
One FSM: The Beta
PC
Q
XADDR
RA1
Memory
RD1
ISEL
JMP(R31,XADDR,XP)
0
1
31:26
25:21
OPCODE
RA
20:5
9:5
4:0
C
RB
RC
+1
0
OPCODE
RA1
Register File
RD1
ASEL
0
RA2
Register File
RD2
SEXT
1 2
1
1
0
A
BSEL
B
ALU
A op B
ALUFN
Z
RA2
Memory
RD2
PCSEL
0
1
D
PC
0
WD
Memory
WA
WE
1
WD
Register File
WEMEM
2
WDSEL
WA
RC
WE
WERF
How Computers Work Lecture 6 Page 2
A generic form of exemplified by the Beta:
The (Synchronous) Finite State Machine (FSM)
IN
Logic
(describable by
truth table)
OUT
NEXT
STATE
CURRENT
STATE
Memory
CLOCK
How Computers Work Lecture 6 Page 3
Another FSM: A (Primitive) Coke
Machine
COKE
1. Coke Costs $0.15
2. Only Nickels + Dimes Accepted
3. FSM Inputs:
5: Nickel
10: Dime
Coke: Give-me-a-coke
Return: Give-me-my-money-back
4. FSM Outputs:
Drop-a-coke (Drop)
Return $.05 (Ret5)
Return $.10 (Ret10)
Return $.15 (Ret15)
How Computers Work Lecture 6 Page 4
State Diagram
for a primitive Coke Machine
How Computers Work Lecture 6 Page 5
Rules for Designing
FSM State Diagrams
• Arcs out of a state must be mutually
exclusive
• Arcs out of a state must be exhaustive (use
* to make this job easier)
• The starting state should be defined
• All possible states should be defined, with
transitions to starting state
• S states requires 2 ^ S state variables
How Computers Work Lecture 6 Page 6
The Synchronous FSM
IN
Comb.
Logic
OUT
NEXT
STATE
CURRENT
STATE
Synch.
Delay
CLOCK
How Computers Work Lecture 6 Page 7
Mealy vs. Moore
MEALY
MOORE
in
out
current
state
next
state
Q
i11,o11
s1
in
out
current
state
next
state
D
Q
D
clk
clk
i21,o21
i21
i12,o12
s2
i22,o22
i11
s1,o1
s2,o2
i22
i12
How Computers Work Lecture 6 Page 8
Mealy vs. Moore
from a Truth Table
CURRENT
STATE IN
NEXT
STATE
OUT
0
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
0
...
0
1
0
1
0
1
0
0
0
1
0
1
1
0
0
0
1
0
...
0
0
1
1
1
1
This is a Mealy machine
How Computers Work Lecture 6 Page 9
Another Way of Drawing
Moore FSMs
Next State
C.L.
in
out
current
state
in
D
next
state
Q
D
Output
C.L.
current state
Q
out
clk
clk
How Computers Work Lecture 6 Page 10
Why do we need the synchronizing
element?
IN
OUT
Logic
STATE
How Computers Work Lecture 6 Page 11
A Human Experiment
Make a power-of-2 sequence generator from 2
adders:
How Computers Work Lecture 6 Page 12
• Experiment 1
–
–
–
–
–
–
Wait your turn
Immediately Look at the two numbers on the board
Immediately Erase the number in front of you
Immediately Add them in your head
Immediately Write the result in front of you
Walk away
• Experiment 2
– Follow the instructions of your sergeant / lecturer
How Computers Work Lecture 6 Page 13
Possible
Synchronizing Elements

The Register, a.k.a. the Edge Triggered FlipFlop
in
out
C.L.
current
state
clk
next
state Q (current state)
Q
D
D (next state)
clk
How Computers Work Lecture 6 Page 14
Edge-Triggered F-F Input Timing
D
CLK
Th = Hold Time
Ts = Setup Time
How Computers Work Lecture 6 Page 15
Possible
Synchronizing Elements
• The Transparent Latch
in
out
C.L.
current
state
next
state
Q
G
Q (current state)
D
G
D (next state)
clk
How Computers Work Lecture 6 Page 16
MUX Implementation
of the Transparent Latch
D
0
D
G
Q
1
G
Q
How Computers Work Lecture 6 Page 17
Input Specifications for the Transparent Latch
D
G
Th = Hold Time
Ts = Setup Time
How Computers Work Lecture 6 Page 18
The Globally Synchronous Discipline
• NO LOGIC CYCLES - All Cycles Are Broken
by at least 1 Synchronizing Delay
• All Synchronizer Inputs obey timing
requirements ( Tsetup, Thold )
How Computers Work Lecture 6 Page 19
Timing Constraints
• Transparent Latch
1
2
G
in
out
3
Logic
4
current state
current
state
next
state
Q
D
G
5
6
next state
Tpd minG-Q < t13
Tpd maxG-Q > t14
Tpd min Logic < t35
Tpd max Logic > t46
clk
t12 < Tpd min G-Q + Tpd min Logic - Thold
How Computers Work Lecture 6 Page 20
Timing Constraints

Edge Triggered Flip-Flop
1
clk
in
out
3
C.L.
4
current state
current
state
next
state
Q
D
5
6
next state
Tpd minG-Q < t13
Tpd maxG-Q > t14
Tpd min Logic < t35
Tpd max Logic > t46
clk
Thold < Tpd minC-Q + Tpd minC.L.
How Computers Work Lecture 6 Page 21
Maximum Frequency
clk
in
C.L.
current
state
out
next
state
Q
D
clk
current state
next state
Clock Period > ___________
T pd max c-q + T pd max cl + T setup
How Computers Work Lecture 6 Page 22
Skew
D
Q
C.L.
D
clk1
Q
clk2
T cd c-q + T cd cl - T hold
Tskew < _______________________________
How Computers Work Lecture 6 Page 23
A Few Details
• What Happens if the Logic has Glitchy Outputs?
in
out
current
state
next
state
Q
D
clk
How Computers Work Lecture 6 Page 24
De-Glitching FSM Outputs
• Assumption: Registers Glitch Free if output doesn’t change
from cycle to cycle.
• Consequence: Output Delayed
in
D
current
state
next
state
Q
Q
out
clk
D
clk
How Computers Work Lecture 6 Page 25
Summary
• Today’s Lecture
– Every modern computer is a finite state machine
– There is a straightforward art to designing FSMs
– Timing is important, but there is a discipline for
insuring correct operation.
• Recitation
– Practical Practice designing and implementing FSMs
How Computers Work Lecture 6 Page 26