TFB hardware status – 5/10/06

update including mods discussed at previous meeting (7/9/06) connectors (power and signals) LV power HV switch LM92 temperature monitoring layout status and ECAL mounting timescale

Mark Raymond - 5/10/06 1

power connector

20 way, dual row, 0.1” pitch MOLEX connector, 3A/pin rated HV HV 1.2

1.2

2.5

2.5

3.3

3.3

5 5 HVgnd HVgnd 1.2gnd

1.2gnd

2.5gnd

2.5gnd

3.3gnd

3.3gnd

5gnd 5gnd some questions (some answers) who provides the cabling – do we make it ourselves?

someone else 48 TFBs per power group – how/where do we split the incoming power lines to feed individual TFBs?

at a distribution module how can we make use of regulator shutdown to disable individual TFBs?

can’t fuses? (regulators include overcurrent/overtemperature protection) could fuse at distribution module?

Shorted SiPM will draw HV current but series resistance will limit to < 1mA can switch off HV (to whole board) and monitor HV current voltages after regulation – actual incoming levels will be higher use 2 pins/supply

Mark Raymond - 5/10/06 2

signal connectors

data screened RJ45 - 4 twisted pairs data in data out 100 MHz clock triggering line (spill start, spill no., cosmic, calibration?) trigger out only one twisted pair/TFB needed use second RJ45 but only one pair merge signals into RJ45 cable to GTM using an intermediate board

Mark Raymond - 5/10/06 3

TFB onboard LV power regulators

supply 1.5 -1.7

3.8

after reg.

component 1.2

LP38843ES-1.2

2.5 A 2.95 - 3.1

2.5 D 3.3 D LP3856ES-2.5

LP3856ES-ADJ current [A] < 3 <0.5

~1.05

~0.95

circuitry supplied FPGA core trip-t FPGA 2.5

FPGA I/O power on TFB [W] 5.1

1.6

3.3

3.6

5.5

5 A LP3856ES-5.0

<0.2

ADCs / HVtrimDACs 1.1

5.7

return

14.7

dropout depends on current – should prob.

take worst case all TO263-5 packages (not proposing to use shutdown I/Ps) incuding regulator power (hopefully worst case) two other small regulators on board to supply PROM (1.8V), slow control cct. (precision 5V), but low power requirements and can take inputs from above supply levels

Mark Raymond - 5/10/06 4

HV switch

HV in 100k BSP225 100 ohms FPGA 100k 1M BSS131 1M ADC I/P 47k GND 1M ADC I/P 47k HV on TFB (to all SiPMs) 0.1uF

prototyped and works OK monitor HV either side of 100 ohms -> crude current measurement 1mA -> 100mV, but resistive division -> only 5mV difference at ADC I/Ps (ADC resolution 1.2 mV) go with this for now, but maybe DC-DC conversion on TFB possible?

Mark Raymond - 5/10/06 5

LM92 temperature sensor

I2C bus acitve when T > programmable limit SDA VS SCL A0 T_CRIT_A A1 GND INT SO8 3.3V

up to 4 I2C addresses (one on board +/- 0.33 deg. accurate around 25 deg. region can mount on small external PCBs for up to 3 external monitoring points 6 wire connector for IDC cable (3.3/GND/SDA/SCL/T_CRIT_A/INT) now on TFB T_CRIT_A and INT open drain so connect all devices in parallel to 2 FPGA I/Ps – 3 ext.) active when T outside programmable window

Mark Raymond - 5/10/06 6

slow control (monitoring)

single channel AD5321 DAC 0 -> 5V, 12 bit resolution, for trip-t electronic calibration 1 2 3 4 5 6 7 8 8 channel AD7998 ADC, 0 -> 5V (power and Vref provided by REF195), 12 bit resolution both chips with I 2 C interface controlled by FPGA allocation of AD7998 inputs 1.2V supply 2.5V supply 3.3V supply 5V supply (divided down) HV before 100 ohms (divided down) HV after 100 ohms (divided down) front end cal voltage spare

Mark Raymond - 5/10/06 7

2 RJ45’s

TFB PCB layout status

coaxial connectors on top surface trip-t, FPGA, HVtrimDACs on bottom (can be thermally coupled to cooling) ADCs, regulators, connectors on top surface I2C connector for external temperature sensors (up to 3) 6 routing layers top, bottom + 4 internal + power and ground layers so maybe 10 layers overall?

signal routing complete

work still to do

power and ground planes

board is now 16 cm in the long direction, 9cm in the short

Mark Raymond - 5/10/06 8

TFB mounting for ECAL

TFB cooled Al mounting plate to SiPM thermal gap filler TFB mounted on cooled Al plate with cutouts through which SiPM cables are fed min. coax connectors (and other connectors) on top surface chips to be cooled on bottom surface, in thermal contact with plate thermal gap filler allows for differences in chip thicknesses power regs. on top side – dissipating heat to board – so will need to provide good thermal pathway to mounting plate in this area of TFB coax socket ~2 mm dia.

terminated coax cable (1.3 mm dia.)

Mark Raymond - 5/10/06 9

cutouts to feed mini coax’s thru to SiPMs data + trig.

TFB mounting for ECAL

6 x 3mm mounting holes 9 cm

Mark Raymond - 5/10/06

16 cm power

10

timescale

still ~1-2 weeks work left on layout most components procured for up to 25 boards only FPGA and PROM (both BGA) non RoHS compliant => 2 step manufacture process still plan to produce 2 boards quickly - hopefully by ~ end October produce more, on slower timescale, after no major (electrical) problems identified testing needs some thought….

Mark Raymond - 5/10/06 11

Mark Raymond - 5/10/06 12

Trip-t and TFB status

Trip-t brief description of internal architecture and interfaces proposed Trip-t operation at T2K SiPM connection, gain and discriminator threshold considerations Results from latest Tript version linearity and discriminator measurements TFB prototype status results from prototyping elements ADC functionality and test results HVtrim functionality and test results Calibration circuitt description and test results TFB layout status TFB firmware status future plans DRAFT TALK – NOT YET FINISHED

Mark Raymond - 5/10/06 13

Trip-t single channel front end architecture

very simplified – neglecting features not relevant to ND280 operation preamp integrate/reset gain adjust 1,2,3,…8 Qin analogue pipeline 1pF 3pF gain 1 or 4 x10 Vth discriminator reset disc. O/P only preamp gain affects signal feeding discriminator – no fine control (x1 or x4) Vth common to all channels on chip analog bias settings, gain, Vth, programmable via serial interface

Mark Raymond - 5/10/06 14

Trip-t full chip

simplified and neglecting features not relevant to operation in ND280 top 16 IP/s 32 front end chans bottom 16 I/Ps 32 analog outputs top 16 disc. O/Ps bottom 16 disc. O/Ps 32 48 analogue memory (pipeline) dig.MUX

32:16 control 32 32:1 analog MUX control top or bottom 16 disc. O/Ps bias, control, reset control serial programming interface, bias gen., control interface, … serial analog output dig.control

32 channel chip -> 1 serial output, 48 deep analogue pipeline to store sampled front end outputs (

note

: pipeline operated using 2 timeslices/preamp integration period, so length reduced to 23 see http://www.hep.ph.ic.ac.uk/~dmray/pdffiles/FIFOtalk_1_3_06 for detailed explanation) have to select either top or bottom 16 disc. O/Ps to transmit off-chip ~ 12 digital control/programming inputs, 16 disc. outputs => ~ 30 I/O lines/chip (2.5 V CMOS)

Mark Raymond - 5/10/06 15

Trip-t operation at T2K

Proposed mode of Trip-t operation for beam spill data acquisition is as follows during spill integrate signal for each bunch and store result in pipeline

*

timestamp high gain channel discriminator outputs that fire (15 timeslices for 15 bunches) after spill continue running in same way, for a while, to catch late signals ( m readout entire contents of pipeline decay) assemble data block containing hit timestamps and all digitized analogue data and transmit transmitting all info in this way allows histogramming of single p.e. events to monitor SiPM gain vast majority of data is pedestal + single/double p.e. hits only start of spill end of spill at this time trip-t switches to inter-spill operational mode (cosmic trigger) 5.25 m s spill period 2.8 m s after spill active period 74 m s (23 cell) readout period (if O/P mux running at 10 MHz)

Mark Raymond - 5/10/06 16

Tript for ND280, gain considerations

need ~ 500 p.e. dynamic range, while simultaneously discriminating signals at the ~ 1p.e. level can’t be done with one gain range => split signal between high/low gain ranges (channels) Signal shared between Cadd, Chi and Clo (also some strays), Chi/Clo = high/low gain ratio trip-t HVglobal

simplified single SiPM channel schematic

1 M W thin coax 50 W SiPM HVtrim Chi 100pF Cadd Clo 10pF 330pF Choose Cadd to match final SiPM gain (330pF about right for 5x10 5 ) Cadd also helps with gain discontinuity when hi gain channel saturates

(see http://www.hep.ph.ic.ac.uk/~dmray/pdffiles/tript_talk_1_3_06)

don’t know what final SiPM gain will be, but assume production devices will be quite well matched in any case will have individual channel gain adjustment by HVtrimDACs

Mark Raymond - 5/10/06 17

Discriminator threshold (Vth) considerations

Qin 1pF analogue pipeline disc. O/P x10 reset Vth Vth only relevant to the 16 high gain channels - remember only 16 channels can be selected for transmission off-chip, so just arrange for these to be the high gain channels (Vth also applied to low gain channels, but we don’t need to look at the outputs of these) Vth needs to be set high enough to prevent single p.e. events triggering discriminator (otherwise single p.e. triggers will dominate and will lose ability to timestamp real signals) uncertainty in threshold setting given by spread in discriminator turn-on curves across chip can choose high gain channel value (external capacitor division ratio)

but

trade-off between threshold adjustment range and uncertainty in threshold value

Mark Raymond - 5/10/06 18

Gain and gain ratio considerations (1)

single tript channel 1pF analogue pipeline Qin x10 disc. O/P reset ~ 1V dynamic range available at preamp O/P Vth ~ similar voltage range at x10 amp O/P ~ similar disc. thresh.

voltage adjustment range 2.5 V CMOS so can assume dynamic ranges of internal circuits ~ 1V this has implications for discriminator threshold range if want 0 – 5 p.e. adjustment range then 5 p.e. ≡ 1V at x10 O/P => 1V ≡ 50 p.e. at preamp O/P so high gain channel will saturate at ~ 50 p.e.

this translates to threshold uncertainty ~ +/- 0.5 p.e. (measured – see later)

Mark Raymond - 5/10/06 19

Gain and gain ratio considerations (2)

Trip-t HV(TFB)

simplified single SiPM channel schematic

1 M W thin coax 50 W SiPM HVtrim So discriminator threshold range adjustment 0 -> 5 p.e.

High gain channel saturates at 50 p.e.

Choose Chi/Clo so low gain channel saturates at 500 p.e.

Chi 100pF Clo 10pF Cadd 330pF

Note

: These values are examples and can change, but need to take care with threshold adjustment range/uncertainty trade-off

Mark Raymond - 5/10/06 20

Latest Trip-t test results from final version

2 nd (final) tript version very similar to 1 st minor architecture change to improve O/P stage linearity version 2 linearity clearly better but still some gain reduction for small signals  will need electronic calibration to correct for linearity 10.5x10

3 10.0

Trip-t V1/V2 linearity comparison 9.5

version 1 version 2 9.0

12 11 10 9 8.5

0

Mark Raymond - 5/10/06

1 2 Qin [pC] 3 4

21

5

4000 3000 2000 higain cahnnels

Tript V2 linearity(1)

all 16 channels, hi and lo gains component values chosen for SiPM gain ~ 5x10 5 (Chi = 100pF Clo=10pF, Cadd=330pF) lo gain saturates at ~ 40 pC (500 p.e.) hi gain saturates at ~ 4 pC (50 p.e.) logain channels 1000 0 0 10 20 30 total external charge injected [pC]

Mark Raymond - 5/10/06

40

22

Tript V2 linearity(2)

1000 8 7 6 5 4 3 2 4 3 2 higain channels logain channels 100 8 7 6 5 4 3 2 10 5 6 7 8 0.1

2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 10 total external charge injected [pC] 2 3 4

Mark Raymond - 5/10/06

log-log plot of same data 10:1 gain ratio means gain range change occurs where logain signal size already large so no S/N problems

23

Tript V2 discriminator measurement

count the no. of times the discriminator fires for 1000 preamp integration periods sweep the injected signal size 1000 800 for 5x10 5 1p.e. -> 0.08 pC 600 pk-pk width ~ 1 p.e. also for this measurment 400 so +/- 0.5 p.e. precision 200 can improve precision but remember trade-off with adjustment range 0 0.00

discriminator curves for all 16 higain channels 0.35

0.05

0.10

0.15

0.20

0.25

1 p.e.

total external charge injected [pC] 2 p.e.

0.30

0.40

Mark Raymond - 5/10/06 24

Tript V2 discriminator timewalk

355 350 345 340 335 330 325 0.0

0.5

1.0

1.5

overall injected charge [pC] 1 2 3 p.e. (1 p.e. = 80 fC (5x10 5 ) ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch8 ch9 ch10 ch11 ch12 ch13 ch14 ch15 significant timewalk and chan to-chan spread for small signals can set threshold at 1.5 p.e. and discriminator will fire, but timestamp for low amplitude signals will not be reliable OK for signals > ~ 3 p.e.

can correct for timewalk off-line 2.0

Mark Raymond - 5/10/06 25

TFB (T

ript

F

ront-end

B

oard)

prototype status

main functionality: 4 Tript’s/TFB => 64 SiPM channels (for ECAL) individual programmable HVtrim (5 V range) for each SiPM channel tript O/P signal digitisation front end electronic calibration FPGA to program tript, sequence operation, timestamp hits, control digitisation, format and transmit data, … local LV power regulation prefer to prototype designs for individual functions as much as poss. before committing to final TFB prototype results here for on-board ADC, HVtrim and electronic calibration circuits

Mark Raymond - 5/10/06 26

prototyping elements of TFB

cal cct AD9201 HVtrimDAC SiPM Tript miniature coax and connectors

necessary to proove as much of TFB circuitry as possible before committing to layout helps to identify where extra layout care is needed improves chances of TFB prototype working successfully

Mark Raymond - 5/10/06 27

SiPM

SiPM -> TFB connection - details

cal test pulse 47k 50V, 0402 47k 50V, 0402 10pF 100V, 0603 HVglobal 51R LV 0603 220pF 50V 0402 significant no. of passives/channel – need careful, high density layout 100pF 100V 0603 trip-t coax sheath

not

DC coupled to GND 1k LV, 0402 HVtrim(0-5V) 100nF LV 0402 330pF 100V 0603 10pF 100V 0603 HVglobal: common to all SiPM channels on TFB HVtrim: individual for each SiPM channel, 5V adjustment range (choice of 8/10/12 bit DAC precision) HVtrim applied to coax sheath – AC but

not

DC coupled to GND

Mark Raymond - 5/10/06 28

Mark Raymond - 5/10/06

ADC for the TFB

AD9201 – used by D-zero dual channel => 2 tript’s/ADC 28 pin SSOP package separate analog and digital supplies 5V analogue – needed to accommodate tript O/P range 3.3 V digital

29

tript linearity measured with AD9201

analog supply and ADC reference voltage configuration optimised so that tript output signals well matched to 10 bit ADC range

Mark Raymond - 5/10/06

1000 900 800 700 600 500 400 300 200 100 0 0 5 high gain channel low gain channel 10 15 20 Qin [pC] 25 30 35

30

40

SiPM signals measured with tript/AD9201

3000 2500 2000 1500 1000 500 0 140 160 180

Mark Raymond - 5/10/06

200 ADC units with LED pulse no LED pulse 220 240 4 2 260 0 14x10 3 12 10 Russian SiPM: gain 5.6x10

5 275 ns preamp integration period 100,000 events in each spectrum ~ 10 ADC units / p.e.

=> 0.1 p.e. ADC resolution 8 6

31

SiPM

HV trim circuit for TFB

HVglobal 51R LV 0603 coax sheath carries HVtrim voltage 1k LV, 0402 HVtrim(0-5V)

Mark Raymond - 5/10/06

100nF LV 0402 8 channel DAC chip => 2 / tript, 8 / TFB 8/10/12 bit versions available identical chips, just different resolution (price difference but negligible to us) TSSOP 16 pin SM package serial interface to program (from FE FPGA) output voltage variable 0 -> 5 V 20 mV resolution for 8 bit version

32

TFB HV trim circuit linearity

5 single DAC channel measurement 4 3 2 1 0 0 50 100 150 DAC value 200 250 0 -2 -4 4 8 bit DAC version used here gives 20 mV precision for 5 V range should be enough?

2

Mark Raymond - 5/10/06 33

TFB HV trim circuit with SiPM

800 600 400 200 0 100 3000 2000 1000 0 100 30 25 20 15 10 5 0 100 DAC value = 0 HVtrim = 0 HV eff. = 50 Volts 300 400 1600 1200 800 500 400 0 100 200 200 DAC value = 100 HVtrim = 2.0 Volts HV effective = 48 Volts 300 400 500 8000 6000 4000 2000 0 100 DAC value = 200 HVtrim = 3.9 Volts HV effective = 46 Volts 200 300 400 500 25 20 15 10 5 0 100 200 DAC value = 50 HVtrim = 1.0 Volts HV eff. = 49 Volts 300 400 500 SiPM LED spectra for device with nominal 47.5 V operating voltage showing effect of HVtrim circuit 5 Volt range for HVtrim gives overall range 45 – 50 Volts (when combined with HVglobal) DAC value = 150 HVtrim = 2.9 Volts HV effective = 47 Volts 200 300 400 500 DAC value = 250 HVtrim = 4.9 Volts HV effective = 45 Volts 200 300 400 500

Mark Raymond - 5/10/06 34

CAL circuit for TFB

10 pF to 16 trip-t SiPM channels before gain splitting capacitors 4 CAL lines feeding every 4 th channel Vcal (0 – 5 V) (use another AD5308 DAC here)

Mark Raymond - 5/10/06

discrete MOSFETs from FE-FPGA

35

2.2

2.0

1.8

1.6

1.4

1.2

1.0

2.2

2.0

1.8

1.6

1.4

1.2

1.0

CAL circuit test results with tript/AD9201

16 high gain chans pedestal DAC val. = 0 DAC val. = 5 DAC val. = 10 DAC val. = 15 DAC val. = 20 DAC val. = 25 tript multiplexed analog output stream for different DAC values for one CAL test input – sampled with scope tript MUX (and ADC) running at 5 MHz 16 low gain chans time [500 ns /division] pedestal DAC=50 DAC=100 DAC=150 DAC=200 DAC=250 substantial crosstalk – but only after high gain channels beyond saturation time [500 ns / division]

Mark Raymond - 5/10/06 36

1000 800

CAL circuit test results with tript/AD9201

linearity measured for one SiPM channel using external test pulse and CAL circuit -> close correspondence (also using AD9201) 600 400 200 high gain / external test pulse low gain / external test pulse high gain / CAL cct low gain / CAL cct 0 0 10 20 Qin [pC]

Mark Raymond - 5/10/06

30 40

37

TFB elements prototyping summary

tript output ADC, SiPM HVtrim DAC circuit and electronic chain calibration circuit all prototyped and tested no major problems encountered can now proceed to lay out the TFB prototype with confidence that at least these elements should function OK.

Mark Raymond - 5/10/06 38

TFB layout status – 10 cm x 16 cm

HVtrim 16 SiPM I/Ps and passives HVtrim Tript AD9201 footprint CAL cct FPGA footprint

high density SiPM I/P layout complete – gives confidence that size target ~ achievable still much left to do (e.g. FPGA dig. signals routing, power regs., connectors (power and control), slow control interface, …..

Mark Raymond - 5/10/06 39

TFB mounting ideas (ECAL)

TFB cooled Al mounting plate to SiPM thermal gap filler TFB mounted on cooled Al plate with cutouts through which SiPM cables are fed min. coax connectors (and other connectors) on top surface chips to be cooled on bottom surface, in thermal contact with plate thermal gap filler allows for differences in chip thicknesses power regs. on top side – dissipating heat to board – so will need to provide good thermal pathway to mounting plate in this area of TFB coax socket ~2 mm dia.

terminated coax cable (1.3 mm dia.)

Mark Raymond - 5/10/06 40

TFB interfaces

4 LVDS pairs (RJ45 type connector and cable – should be screened) Clocks input: Data input Data output 100 MHz, 1Hz, Spill/Cosmic trigger RF clock ? (maybe not needed) slow control TBD (maybe just a connector to plug-on micro-controller based circuit?) Power < ~100V +2.5

+ 5 +3.3 +1.2

small ~ 0.5A ~ 0.2A

TBD TBD SiPM HV tript and FPGA I/O ADC analogue and HVtrim DAC ADC digital and FPGA I/O FPGA core

Mark Raymond - 5/10/06 41

some data volume numbers

for programming tript: ~ 900 kbits for 50k channels HVtrim DACs: 8 bits res’n x 50k chans = 400 kbits for raw spill data readout (data only) assume 23 integration periods 4 tript’s / TFB 32 channels/tript (hi and logain) 10 bit ADC => ~30k bits /TFB /spill + hit timestamp data and associated hit channel addresses

Mark Raymond - 5/10/06 42

planning

Plans for this year (2006) 1 st TFB prototype to be produced by end October in parallel produce sufficient firmware for characterization detailed electrical characterization by beginning 2007 Plans for next year (2007) vertical slice test (1 st quarter) TFB prototype with photosensors, RMM and MCM prototypes review requirements and design 2 nd (final) TFB prototype for ECAL produced and tested by end of year

Mark Raymond - 5/10/06 43