Transcript Document

Trip-t and TFB status
Trip-t
schematics
Trip-t operation at T2K
SiPM connection and gain considerations
Latest results from version 2 – the final version
TFB
conceptual layout
interfaces
components
electronic calibration
data volumes
plans for this year
Mark Raymond - 28/04/06
1
Trip-t schematics - overview
trigger pipeline column
prior to readout
SKIPB
not used
A-Pipeline
48 x 32 chan
Q_TEST [0:32]
Analog
MUX
Front End
Q_IN [0:32]
32 inputs
Dummy OUT [33]
t-Pipeline
48 x 32 chan
PROG_CTRL
PROG_CLOCK
Analog
MUX
t
not used
OUT
mux control
MUX_CLK
signals MUX_RESET
PROG_IN
PROG_RESET
serial analogue output
A OUT
Prog
Interface
DAC
OUT
DISCRIM [0:31]
PROG_OUT
programming
interface
DISC_OUT[0:15]
Digital
MUX
DIG_EN_L
DIG_EN_U
DIG_RESET
select which group of 16 to output
reset during preamp reset period
taken from Bench test of TRIP-t, Leo Bellantoni, Paul Rubinov, D0 note ##v4
Mark Raymond - 28/04/06
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Trip-t schematics – front end
don’t use
IBOPAMP
A OUTPUT
-
to pipeline
IBOPAMP
200fF
preamp
+
-
GAIN[2]
160fF
GAIN[1]
80fF
80fF
V_REF
+
Q_IN
set to zero to avoid
linearity discontinuity
IFFP2
IBP
1.0 pF
GAIN[0]
40f
F
IB_T
t OUTPUT
not used
3.0 pF
40fF
GAIN[3]
Z
IBCOMP
IBOPAMP
IFF
x10
V_TH
x10
-
RESET
V_REF
IFFP2
+
PLN_CLK
+
disc.
thresh
DISCRIM_OUT
taken from Bench test of TRIP-t, Leo Bellantoni, Paul Rubinov, D0 note ##v4
Mark Raymond - 28/04/06
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Trip-t operation at T2K
The proposed mode of Trip-t operation for beam spill data acquisition is as follows
during spill
integrate signal for each bunch and store result in pipeline* (15 timeslices for 15 bunches)
timestamp high gain channel discriminator outputs that fire and store
after spill
continue running in same way, for a while, to catch late signals (m decay)
readout entire contents of pipeline
assemble data block containing hit timestamps and all digitized analogue data and transmit
transmitting all info in this way allows histogramming of single p.e. events to monitor SiPM gain
vast majority of data is pedestal + single/double p.e. hits only
start of spill
5.25 ms
spill period
end of spill
2.8 ms
after spill
active period
74 ms (23 cell) readout period
(if O/P mux running at 10 MHz)
at this time trip-t switches
to inter-spill operational mode
(cosmic trigger)
*Note: pipeline operated using 2 timeslices/preamp integration period to avoid FIFO overflow
problem, so pipeline length reduced to 24
(explained in http://www.hep.ph.ic.ac.uk/~dmray/pdffiles/FIFOtalk_1_3_06)
Mark Raymond - 28/04/06
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SiPM connection
HV(TFB)
trip-t
100pF
1 MW
thin coax
50W
10pF
SiPM
HVtrim
330pF
short length (~20 cm) coax between SiPM and tript
SiPM connected between core and coax sheath (core carries bias voltage)
50W provides some kind of termination for the cable
charge split between two tript channels using different capacitor values to get high/low gain
Mark Raymond - 28/04/06
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Gain considerations
don’t know what final SiPM gain will be, but assume production devices will be quite well matched
in any case will have individual channel gain adjustment by HVtrimDACs
Signal shared between Cadd, Chi and Clo (also some strays)
Choose Cadd to match final SiPM gain (330pF about right for 5x105)
Cadd also helps with gain discontinuity when hi gain channel saturates
(see http://www.hep.ph.ic.ac.uk/~dmray/pdffiles/tript_talk_1_3_06)
HV(TFB)
Chi
100pF
trip-t
1 MW
thin coax
50W
Clo
10pF
SiPM
HVtrim
Mark Raymond - 28/04/06
Cadd
330pF
6
Gain ratio considerations
1pF
analogue
pipeline
Qin
x10
reset
disc. O/P
Vth
aim for fullscale signal capability (logain channel) of 500 p.e.
(e.g. 40 pC for 5x105 SiPM gain)
let’s assume want discriminator threshold adjustment range 0 – 5 p.e.
trade-off between range and threshold adjustment precision here
(see http://www.hep.ph.ic.ac.uk/~dmray/pdffiles/tript_talk_1_3_06)
fixed x10 gain stage between preamp and comparator means higain fullscale ~ 50 p.e.
so hi:lo gain ratio 10:1
HV(TFB)
Chi
100pF
trip-t
1 MW
thin coax
50W
Clo
10pF
SiPM
HVtrim
Mark Raymond - 28/04/06
Cadd
330pF
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Latest Trip-t test results from final version
LabVIEW
VME
Programmable
Digital Pattern
Generator
prog.
attenuator
ck and trig.
ADC
~14 control lines
preamp int./reset
pipeline, multiplexer,
programming
level shift
dECL ->
2.5V CMOS
Qinj
Mark Raymond - 28/04/06
Trip-t
Scope
8
Photos
Trip-t board
dECL -> 2.5 V CMOS
level shift
ADC
digital pattern generator
dECL outputs
Mark Raymond - 28/04/06
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Tript V1 v. V2 linearity
12
Trip-t V1/V2 linearity comparison
3
10.5x10
version 2 linearity better but still
some gain reduction for small
signals
=> will need calibration
11
3
x10
ADC units
10.0
10
9.5
version 1
version 2
9.0
9
8.5
0
1
2
3
4
5
Qin [pC]
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Tript V2 linearity
4000
all 16 channels, hi and lo gains
component values as on p. 6/7
lo gain saturates at ~ 40 pC
3000
ADC units
hi gain saturates at ~ 4 pC
2000
1000
0
0
10
20
30
40
total external charge injected [pC]
Mark Raymond - 28/04/06
11
Tript V2 linearity
4
log-log plot of same data
3
2
10:1 gain ratio means gain range
change occurs where logain signal
size already large so no S/N problems
1000
8
7
6
5
ADC units
4
3
2
100
8
7
6
5
4
3
2
10
5 6 78
2
3
4
5 6 78
0.1
2
3
4
5 6 78
1
2
3
4
10
total external charge injected [pC]
Mark Raymond - 28/04/06
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Tript V2 discriminator measurement
discriminator curves for all 16 higain channels
count the no. of times the discriminator fires
for 1000 preamp integration periods
sweep the injected signal size
# of times disc. fires
for 5x105 1p.e. -> 0.08 pC
1000
pk-pk width ~ 1 p.e. also for this measurment
so +/- 0.5 p.e. precision
can improve but trade-off with adjustment range
800
600
400
200
0
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
total external charge injected [pC]
1 p.e.
Mark Raymond - 28/04/06
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0.40
Tript V2 discriminator timewalk
average discriminator firing time [nsec]
355
ch0
ch1
ch2
ch3
ch4
ch5
ch6
ch7
ch8
ch9
ch10
ch11
ch12
ch13
ch14
ch15
350
345
340
335
large timewalk and
chan-to-chan spread for
small signals
OK for signals > ~ 3 p.e.
could improve but once again
trade-off with discriminator
adjustment range
330
325
0.0
0.5
1.0
1.5
2.0
overall injected charge [pC]
1 p.e. = 80 fC
Mark Raymond - 28/04/06
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SiPM/tript version 2 results
Russian SiPM (CPTA – 600 pixels)
39 V bias
2000
higain channel
led pulsed during
preamp integrate period
-> red distribution
get blue distribution when led
switched off -> can see 1 and 2 p.e.
peaks
1500
counts
preamp integrate:reset ratio
325ns:75ns
3000
2000
1000
1000
500
0
8000
0
8100
8200
8300
8400
8500
8600
8700
8800
8900
9000
ADC units
Mark Raymond - 28/04/06
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TFB – Trip-t Front end Board
aiming for 10 cm x 15 cm
cal dac
trip-t
HVtrim
16 x SiPM connectors
16 x SiPM connectors
HVtrim
trip-t
ADC
HVtrim
DAQ
I/F
FE-FPGA
this picture is conceptual – reality will be
different – but we need to decide what
the reality should be in the near future
power
HVtrim
HVtrim
trip-t
HVtrim
Mark Raymond - 28/04/06
16 x SiPM connectors
ADC
trip-t
cal dac
real layout only just beginning on
analogue front end interface
need to keep component density high
here and take care of signals
propose to use ultra-min. coax connectors
SiPM connection needs thought
HVtrim
local
supply
and T
monitoring
16 x SiPM connectors
picture shows conceptual layout of
main components
need to consider cable routing, how
connections can be made, cooling …
HVtrim
16
Trip-t pinout
128 pin 14 x 14 mm2
QFP
Mark Raymond - 28/04/06
analog I/Ps
digital disc O/Ps
digital control I/Ps
analog test I/P
analog bias (dec.)
analog O/P
test I/P only
+2.5V
gnd
not used
17
Trip-t control signals
Programming interface and O/P mux control
PrgReset
resets programming interface
PrgCtrl
defines whether programming the chip or running the output MUX
PrgIn
serial programming info or MUX reset (depending on PrgCtrl)
PrgOut
serial output to read back programmed register values
PrgClk
shift in serial programming data or MUX clock (depending on PrgCtrl)
some dual
functionality
here
Pipeline control and triggering
PlnReset
Resets the pipeline
PlnClk
Pipeline clock
SkipB
Triggers the pipeline (stops timeslice of interest being overwritten)
PR1
Initiates pipeline readout (validated by PlnClk edge)
MoveData Clears triggered pipeline column (allows timeslice to be overwritten – validated
by PlnClk edge)
Preamp integrate/reset cycling
PreReset
Switches preamplifiers between integrate/reset
Pre2aReset complement of PreReset
Pre2bReset complement of PreReset
Discriminator outputs enable and reset
DigenL
enables one bank of 16 discriminator outputs off-chip (fixed level)
DigenU
enables the other bank (fixed level)
DigResetB resets the discriminators (do this during preamp reset period)
14 – 16 control lines depending on whether we fix DigenL/DigenU or leave programmable
Mark Raymond - 28/04/06
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Trip-t registers
serial programming interface
chip ID: 01010
register address: 5 bits
operation: 3 bits (read/write/set/reset/default)
1 bit space
value: 8/10/34 bits
~ 300 bits to send to fully
program chip
so for 50k channels, ~3000 trip-t’s
need ~ 900k bits (not that much)
 initialising the system from scratch
will not take any significant time
Mark Raymond - 28/04/06
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ADC and HVtrimDAC
ADC
D0 uses AD9201 – seems suitable for us too
dual channel, 20 MHz, 10-bit, single supply (2.7 V min.)
parallel O/P but 2 channels data multiplexed onto single 10-bit bus
215 mW (+3V supply)
HVtrimDAC
propose AD5308
8 channel (2/trip-t), buffered outputs, single supply (2.5V min.)
serial load
8 bits res’n (could use 10 or 12 bit versions)
propose to prototype the use of these chips in conjunction with trip-t test board before
committing to TFB layout
Mark Raymond - 28/04/06
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TFB Trip-t I/O
4 cal lines
FE-FPGA digital IO per pair of Trip-T’s
16 disc.O/P’s
16 SiPM’s
TRIP-T
14 control
4 HVtrim control (2 HVtrimDACs)
HVtrim
((4+16+14+4)x2) + 12 = 88
assuming all control lines independent
(some could be shared between trip-t’s
but would lead to more complicated
pcb track routing)
4 Trip-t’s per TFB => 176 total
2 ADC control
10 bits
4 cal lines
more lines required for:
local T and supply voltage monitoring
cal level generation
off-board communication
…..
16 disc.O/P’s
16 SiPM’s
TRIP-T
14 control
4 HVtrim control (2 HVtrimDACs)
HVtrim
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electronic chain calibration
propose something like
to 16 trip-t SiPM channels
before gain splitting capacitors
every 4th channel
Vcal
(need another
DAC here)
from FE-FPGA
needs to be prototyped – provision to do this included on trip-t test board
Mark Raymond - 28/04/06
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TFB interfaces
4 LVDS pairs
Clocks input:
Data input
Data output
RF clock
100 MHz, 1Hz, Spill/Cosmic trigger
programming setup (trip-t, HVtrim, CAL levels)
read back, spill data, cosmic trigger out, monitoring data, …
synchronization to beam
Power
SiPM HV
+2.5 (tript, HVtrimDACs and FPGA)
+3.3 (ADC, FPGA)
other levels may be necessary?
Mark Raymond - 28/04/06
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some data volume numbers
for programming
tript: ~ 900 kbits for 50k channels
HVtrim DACs: 8 bits res’n x 50k chans = 400 kbits
for raw spill data readout (data only)
assume
23 integration periods
4 tript’s / TFB
32 channels/tript (hi and logain)
10 bit ADC
=> ~30k bits /TFB /spill
+ hit timestamp data and associated hit channel addresses
Mark Raymond - 28/04/06
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TFB FE-FPGA tasks
Clock and trigger recovery and synchronization - 100 MHz / RF clock / spill trigger / cosmic trigger
Tript register programming
SiPM HV-trim - individual HV trim DACs on all SiPM channels need programming
Tript and ADC operation sequencing during spill - digital control signals for integrate/reset, pipeline
write cycling, pipeline read, output mux cycling and ADC control and readout
Hit timestamping (linked to above) - timestamp tript discriminator outputs to 2.5 ns precision
Data formatting and transmission - bundle up timestamp information and digitized analogue data
into agreed fromat and transmit
Cosmic trigger formation - during spill gaps (~ 3 secs) need to cycle chip, look for patterns of
discriminator hits from neighbouring channels, transmit trigger off-board, respond with data if trigger
returned
local monitoring – temperature, local voltage levels
electronic calibration – outside normal physics data taking
Mark Raymond - 28/04/06
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plans for this year
complete tests with trip-t test board
calibration cct
ADC
HVtrimDAC
other things to define
what to monitor locally and how to implement it
1st TFB prototype to be produced by October
in parallel produce firmware to implement main functionality
detailed electrical characterization by end of year
Mark Raymond - 28/04/06
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