Transcript Document

Trip-t & TFB
Trip-t
schematics
signals and registers
operation
SiPM connection
TFB
block diagram
functionality (slow control and FE-FPGA)
Mark Raymond - [email protected] - 16/12/05
1
Trip-t schematics - overview
from “Bench test of TRIP-t”
Leo Bellantoni & Paul Rubinov
SKIPB
A-Pipeline
48 x 32 chan
Q_TEST [0:32]
Analog
MUX
A OUT
Front End
Q_IN [0:32]
Dummy OUT [33]
t-Pipeline
48 x 32 chan
OUT
MUX_RESET
PROG_CTRL
PROG_CLOCK
t
MUX_CLK
PROG_IN
PROG_RESET
Analog
MUX
Prog
Interface
DAC
OUT
DISCRIM [0:31]
PROG_OUT
DISC_OUT[0:15]
Digital
MUX
DIG_EN_L
DIG_EN_U
DIG_RESET
Mark Raymond - [email protected] - 16/12/05
2
Trip-t schematics – front end
from “Bench test of TRIP-t”
Leo Bellantoni & Paul Rubinov
IBOPAMP
A OUTPUT
IBOPAMP
200fF
+
-
GAIN[2]
160fF
GAIN[1]
80fF
80fF
V_REF
+
Q_IN
IFFP2
IBP
1.0 pF
GAIN[0]
40f
F
IB_T
t OUTPUT
3.0 pF
40fF
GAIN[3]
Z
IBCOMP
IBOPAMP
V_TH
IFF
x10
-
RESET
V_REF
+
+
PLN_CLK
DISCRIM_OUT
IFFP2
only 2 gain settings to preamp (1 & 4)
preamp output goes straight to discriminator (global threshold)
could be awkward if widely varying SiPM gains
other gain settings only affect signals to pipeline
Mark Raymond - [email protected] - 16/12/05
3
Trip-t pinout
128 pin 14 x 14 mm
QFP
Mark Raymond - [email protected] - 16/12/05
analog I/Ps
digital disc O/Ps
digital control I/Ps
analog test I/P
analog bias (dec.)
analog O/P
test I/P only
+2.5V
gnd
not used
4
Trip-t control signals
PrgReset
PrgCtrl
PrgIn
PrgOut
PrgClk
resets programming interface
defines whether programming the chip or running the output MUX
serial programming info or MUX reset (depending on PrgCtrl)
serial output to read back programmed register values
shift in serial programming data or MUX clock (depending on PrgCtrl)
PR1
PlnClk
PlnReset
MoveData
SkipB
PR2
Triggers pipeline readout
Pipeline clock
Resets the pipeline
Clears triggered pipeline column (allows timeslice to be overwritten)
Triggers the pipeline (stops timeslice of interest being overwritten)
Pipeline pedestal acquisition (not used – left over from SVX)
dual fast/slow
functionality here
PreReset Switches preamplifiers between integrate/reset
Pre2aReset complement of PreReset
Pre2bReset complement of PreReset
DigenL
enables one bank of 16 discriminator outputs off-chip
DigenU
enables the other bank
DigResetB resets the discriminators
Mark Raymond - [email protected] - 16/12/05
5
Trip-t registers
programming
chip ID: 01010
register address: 5 bits
operation: 3 bits (read/write/set/reset/default)
1 bit space
value: 8/10/34 bits
Mark Raymond - [email protected] - 16/12/05
6
Trip-t operation during spill
beam bunches
end of
spill
event
PlnReset
PreReset
PlnClk
discriminator fires
programmed bunch latency
need to continue clocking
pipeline beyond end of spill
until latency has elapsed
(might be an event in last
bunch)
SkipB
PlnClk transfers preamp output to pipeline at end of integration period
Pipeline internal write (and trigger) pointer then advances to next timeslice
Pipeline trigger pointer points to timeslice that was written the programmed bunch latency before
When SkipB applied the timeslice that the trigger pointer is pointing to is marked to not be overwritten
(the write pointer will skip over it the next time it comes round)
and its address is stored in a fifo (only 4 deep)
only 4 timeslices can be triggered in a particular spill
(you can return triggered timeslices to normal operation by applying MoveData signal after the timeslice data
have been MUXed out, so could continuosly trigger and read out chip, but taking care not to have more than
4 triggered timeslices in the pipeline at any one time)
Mark Raymond - [email protected] - 16/12/05
7
At end of spill
run the MUX
MUX reset, and then MUX clock
simultaneously control ADC
clock and ADC output MUX (2 ADC channels share 10 bit O/P parallel data bus)
specified (D0) ADC can run at 20 MHz
=>1 timeslice can be read out in 32 x 50 ns = 1.6 usec (+ a bit for MUX reset)
don’t necessarily have to wait till end of spill, could run MUX and Preamp/Pipeline simultaneously
just have to take care not to overtrigger (fifo depth)
but may be preferable to have separate acquisition/readout phases
Mark Raymond - [email protected] - 16/12/05
8
SiPM connection
connection method
Vbias
trip-t
3p3
1 MW
thin coax
or twisted pair
50W
LED
330p
SiPM
feed in small
current here to tune Vbias for
individual SiPM’s
SiPM -> Tript cable: have used coax mostly up to now
SiPM connected between core and coax sheath (core carries bias voltage)
Coax provides signal shielding, twisted pair doesn’t – could we use shielded twisted pair?
50W provides some kind of termination for the cable (-> 100W for twisted pair)
charge split between two tript channels using different capacitor values to get high/low gain
Mark Raymond - [email protected] - 16/12/05
9
SiPM connection (analogue issues)
high gain channel
3
10.5x10
ADC units
IBT=80
IBT=0
10.0
9.5
low gain channel
9.0
8.5
0
2
4
6
8
10
12
14
Qin [pC]
Tript with high preamp gain setting (1pF feedback)
high gain saturates at ~ 1pC, low gain at ~ 15 pC (for charge splitting cap. values on p. 10)
can we use SiPM HV trim to tune individual SiPM gains to match these ranges?
how well will final SiPM gains have to match?
how well do SiPM gains really have to match?
Mark Raymond - [email protected] - 16/12/05
10
TFB
HVTrimDAC
SiPM
x16
8
8
local power conditioning
TripT
HVTrimDAC
ADC
HVTrimDAC
SiPM
x16
8
8
TripT
timing
HVTrimDAC
FE-FPGA
HVTrimDAC
SiPM
x16
8
8
TripT
HVTrimDAC
ADC
HVTrimDAC
SiPM
x16
8
8
fast serial data
TripT
temperature monitoring
low voltage monitoring
high voltage monitoring
calibration
mcontroller
slow serial I/F
HVTrimDAC
Mark Raymond - [email protected] - 16/12/05
11
micro-controller functionality (slow control)
•looks after programming of front end chips (internal LUT contains operational values)
at power on, and on external request
needs to communicate with FE-FPGA
- Tript programming inputs share pins with MUX control signals
•monitor local (TFB) low and high (for TFB, not for every SiPM) voltage levels using internal, multi-input ADC
•monitor local environment (obviously temperature but anything else…?)
may need external sensors
•Trip-t & electronic chain calibration (independent of SiPM)
using Tript input channel mask register and external DAC can inject programmable
amplitude test pulses into individual channels
need to synchronize with FE-FPGA
•slow interface to outside – could be custom, could be commercial (e.g. I2C?)
•generate alarm (e.g. over-temperature)
•will we want to be able to re-program micro-controller in TFB production version?
•clearly this functionality could be implemented in FE-FPGA
would then need extra service chips (at least a multi-channel ADC)
keeping data and control paths separate usually considered good thing
Mark Raymond - [email protected] - 16/12/05
12
FE-FPGA functionality (fast control)
•Synchronization to accelerator (spill structure and bunch clock) (how?)
•Tript operation during spill
provide clocks (preamp integrate/reset and pipeline)
timestamp discriminator outputs and return trigger (SkipB) to mark pipeline timeslices to
be subsequently read out (max 4 per spill (depth of Tript FIFO))
•At end of spill (after pipeline latency elapsed)
Run Tript MUX and ADC to read out triggered timeslices
acquire digitized data
time required
= 32 x no. of triggers x mux clock period (50ns say)
= 1.6 usec x no. of triggers
format data and transmit (later slide)
•During spill gap (~ 3 secs.) look for cosmics
free run Tript – continuous pipeline cycling
trigger in same way as during spill, but also pass triggers off board
(do we need to construct local track trigger?)
(do we need to wait for return of trigger accept signal from outside?)
Run MUX and ADC for every trigger, format data and transmit
should be able to be live for high percentage of time (trigger rate << 1 per 1.6 usec)
Mark Raymond - [email protected] - 16/12/05
13
What to do with spill (and cosmic) data in FE-FPGA? – some options here
1) minimal processing
attach timestamp, bunch no., individual TFB ID, raw data and transmit everything
(will want option to operate in this mode for debugging)
2) more processing
pedestal subtract, suppress channels with no signal (vast majority), attach timestamp,
bunch no, individual SiPM no., individual TFB ID, signal amplitude, and transmit
Where / how / how often to construct s.p.e. spectra for SiPM gain calibration?
does this need to be done in FE-FPGA?
- complicated thing to have to do
comes with raw data anyway
- s.p.e. noise hits in channels without
signal
signal counts
1500
could locally generate dummy triggers at
some rate but may conflict with cosmic
event acceptance
3
60x10
1000
40
led
noise only
500
20
0
Mark Raymond - [email protected] - 16/12/05
8.5
0
9.0
9.5
ADC units
3
10.0x10
14
noise counts
could insist on raw data transmission
outside spill time (make this an offdetector task?)
R1 (0509-023)
39.0 V bias
11/11/05