Computer Architecture Lecture 2
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Transcript Computer Architecture Lecture 2
Computer Architecture
Lecture 2
Abhinav Agarwal
Veeramani V.
Quick Recap
Various metrics in design of processor
The interface & internal structure
Instruction Set Architecture
Assembly instructions
Instruction encoding
add r1, r2, r3
000111
00001
00010
00011
Outline
RISC
Multi-cycle execution
Pipelining
Reduced Instruction Set Computer (RISC)
Limited no. of instructions
Fixed Length
Simple to decode
Easier to implement in hardware
Prevalent in all commercial processors at the core
level
Counterpart – C(omplex)ISC
Intel processors
Multi-operation instructions
Still Intel processors have switched to RISC at second level
Execution Cycle of a RISC
Instruction
Five main phases of Instruction Lifecycle
IF: Instruction Fetch
1.
Read Instruction Memory at PC
Bring the instruction into the CPU
ID/RF: Instruction Decode/Register Fetch
2.
Translate the opcode of the instruction to appropriate control
signals
No. of operands
Registers clearly specified in instruction code
Fetch operand values from the registers
Execution Cycle of a RISC
Instruction
EX: ALU computation
3.
Activate appropriate functional unit – Adder, Multiplier, Divider,
Logical Unit
Why no Subtracter?
MEM: Memory Operation
4.
Load/Store data from/to Data Memory
WR: Register Write
5.
Write the final result value into register
A Picture speaks a thousand words
Multi Cycle Execution
Cycle Per Instruction (CPI)
Kinds of Implementation:
1.
One cycle for each stage
2.
Cycle time determined by longest stage
CPI = ?
Combine all stages into a single cycle
Cycle time determined by worst case instruction
CPI = 1
Execution Snapshot: Cycle 1 IF
PC
00010
Instr
00000
Mov r2, 2A
00001
Mov r3, 12
00010
Add r1,r2,r3
00011
Store r1,0(r4)
00100
XXXX
00101
XXXX
000111 00001 00010 00011
Address
Execution Snapshot: Cycle 2 ID/RF
PC
00011
00001
Mov
00010
add
00011
Store
00100
XXXX
00101
XXXX
r2,
Mov
r1,
00000
Add
Instr
r3
000111 00001 00010 00011
Address
Reg
Data
r1
12 H
r2
2A H
r3
12 H
r4
00 H
r5
01 H
Execution Snapshot: Cycle 3 EX
PC
00011
00001
Mov
00010
add
00011
Store
00100
XXXX
00101
XXXX
Data
r1
12 H
r2
2A H
r3
12 H
r4
00 H
r5
01 H
12
Adder
r2,
Mov
r1,
00000
Add
Instr
r3
000111 00001 00010 00011
Address
Reg
2A
Execution Snapshot: Cycle 4 MEM
PC
00011
00001
Mov
00010
add
00011
Store
00100
XXXX
00101
XXXX
Data
r1
12 H
r2
2A H
r3
12 H
r4
00 H
r5
01 H
12
2A
Adder
r2,
Mov
r1,
00000
Add
Instr
r3
000111 00001 00010 00011
Address
Reg
??
Execution Snapshot: Cycle 5 WB
PC
00011
00001
Mov
00010
add
00011
Store
00100
XXXX
00101
XXXX
Data
r1
3C H
r2
2A H
r3
12 H
r4
00 H
r5
01 H
Adder
r2,
Mov
r1,
00000
Add
Instr
r3
000111 00001 00010 00011
Address
Reg
Execution Snapshot: Cycle 1 IF
PC
00011
00001
Mov
00010
add
00011
Store
00100
XXXX
00101
XXXX
0(r4)
Mov
r1,
00000
store
Instr
111001 00001 00100 00000
Address
Instruction Execution Timeline
Sequential Execution
Low utilization of functional units
Alternative ?
store r1, 0(r4)
add r1, r2, r3
IF
ID/
RF
EX
ME
M
WB
IF
ID/
RF
EX
ME
M
Instruction Execution Timeline
IF
ID/
RF
EX
ME WB
M
Pipelining: Concept and Example
Washing machine, Dryer, Iron
source: http://cse.stanford.edu/class/sophomore-college/projects-00/risc/pipelining/
Pipelining Concept
Remarkable Insight or Common Sense
Time Savings:
Per person
0%
Overall
42%
source: http://cse.stanford.edu/class/sophomore-college/projects-00/risc/pipelining/
Implementation of Pipelining in RISC
Parallelism in all 5 stages
New instruction every cycle
Best case scenario
Inst
IF
Time
ID/RF EX
MEM WB
IF
ID/RF EX
MEM WB
IF
ID/RF EX
MEM WB
IF
ID/RF EX
MEM WB
IF
ID/RF EX
MEM
WB
Hardware Requirements
source: http://cse.stanford.edu/class/sophomore-college/projects-00/risc/pipelining/
Problems
Data hazards
Dependent Instructions
IF
ID/RF EX
MEM WB
IF
ID/RF EX
MEM
WB
Control Hazards
Branches resolution
add r1, r2, r3
store r1, 0(r4)
bnz r1, label
add r1, r2, r3
label: sub r1, r2, r3
Structural Hazards
IF
ID/RF
EX
MEM
WB
IF
ID/RF
EX
MEM
WB
IF
ID/RF
EX
MEM
WB
References
Wikipedia: CPU Parallelism
http://en.wikipedia.org/wiki/Central_processing_unit#Parallelism
http://www.cs.iastate.edu/~prabhu/Tutorial/PIPELINE/pipe_title.html