Transcript Floating point processor for Programmable calculator

Floating point processor for
Programmable calculator
Vikas Kumar Sharma
Saurabh Gupta
Mentors: Veeramani V., Abhinav Agarwal
June 14, 2006
EE Summer Camp 2006
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Outline
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IEEE 754 standard
Floating Point Arithmetic
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Processor Design
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Addition & Subtraction
Multiplication & Division
Exceptions
Instruction Set Architecture (ISA)
Processor units
FPGA implementation
Conclusion
Future work
References
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EE Summer Camp 2006
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Introduction
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Floating point Calculator design
Standard used: IEEE 754
Operations implemented: - Addition,
Subtraction, Multiplication, Division
User programs in hex using simple assembly
instructions
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IEEE 754 standard
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Single precision
Sign bit
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0 – Positive
1 – Negative
Exponent: Biased by 127
Fraction: implicit ‘1’ excluded from mantissa
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Zero & Infinity
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Zero & Infinity are represented by a special
values
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0_00000000_00000000000000000000000
represents 0 and not (1.0)*2^(-127)
0_11111111_00000000000000000000000
represents ∞ and not (1.0)*2^(128)
Arithmetic needs to be handled separately
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Arithmetic Algorithms
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Addition
Subtraction
Multiplication
Division
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Addition & Subtraction
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Multiplication & Division
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Normalization to IEEE 754
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0.0000101000000… * 2^(128)
Normalized as 1.010000… * 2^(123)
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How?
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We need implicit ‘1’ in the IEEE 754 format
Leading Zero Counter
Barrel Shifter
Both these modules are combinatorial
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Leading Zeros Counter
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Barrel Shifter
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Exceptions Behavior
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Exceptions Implemented
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Out of Bound
Invalid operation
Operation suspended & FPGA LED blink
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Processor Design – ISA
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Register File
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32-bit – IEEE 754 format
8 registers – sufficient for fairly complex operations
16-bit Instruction code
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Opcode
Destination register address
Source Address 1
Source Address 2
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Instructions
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Arithmetic operations – 16 bit, 3 register
addresses
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Add
Subtract
Multiply
Divide
Move – 48 bit, 1 register address
Termination instruction – 16 bit, all zeros
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Processor Units
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Processor Units…
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Instruction Fetch Unit (IF)
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Starts on reset with counter value zero
Fetches instruction to decoder or register file
depending on the instruction type
Instruction Decode Unit (ID)
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Starts at the finish of IF
Passes proper ALU unit code to execution module
and register addresses to register file
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Processor Units…
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Execution Unit (EX)
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Starts at the data read signal from register file
Operands passed to FPU with a activation signal to
the required arithmetic unit
Gives the result to Write Back Unit in IEEE 754 format
Write Back Unit (WB)
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Starts at the finished execution signal from EX
Selects between the result and the input data
depending upon the instruction code
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Simulation of FPU
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Appropriate test benches were used for
simulation and design was verified
Exception behavior was checked
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Simulation of Processor
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Expression to calculate
(((1.75)/(1.5-1.75))*2.5)+((1.5-1.75)/2.5)=
-17.6
Corresponding instruction set:
Move r0, 1.5
Move r1, 1.75
Sub r2, r0, r1
Div r3, r1, r2
Move r4, 2.5
Mult r5, r3, r4
Div r6, r2, r4
Add r7, r5 , r6
000000000…00000
Result by Simulation = -17.60000229
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FPGA implementation of FPU
AdditionSubtraction
Multiplication
Division
Complete
Processor
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Logic elements
used
Memory bits
used
Clock cycles
used
6
0
4
1202
8896
33
685
0
54
5330
21568
--
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FPGA Implementation of processor units
Processor Unit
Clock cycles used
(simulation result)
Instruction Fetch Unit
1
Instruction Decode Unit
2
Register File Read
1
Write Back Unit
2
Register File Write
1
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Conclusion
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FPU unit implemented on FPGA successfully
Complete Processor simulated and
synthesized successfully
Optimization required in some parts
Critical issues in synthesis were understood
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Future work
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Double precision
Jump and branch operations
Square Root calculation
Optimization
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References
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Institute of Electrical and Electronics Engineers, ”IEEE
Standard for Binary Floating-Point Arithmetic”,
ANSI/IEEE Standard 754-1985, August 1985
http://docs.sun.com/source/806-3568/ncg
goldberg.html
http://en.wikipedia.org/wiki/Booth’s multiplication
algorithm
http://www.cs.wisc.edu/
smoler/x86text/lect.notes/arith.flpt.html
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Thank you
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