Transcript MODERN presentation template

Task 5.2: Demonstrator design, implementation and
characterization
Objectives: develop and implement demonstrator chips related to the
major activities carried on the other work-packages
Activities as described in Technical Annex:
Test-chip activities:
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Level shifter circuits, basic circuits implemented with regular layout (UPC)
PV aware and lifetime-critical circuits (TUGI)
Substrate noise (NXP)
PV aware monitors/controls for self-timed logic (LETI)
compensation schemes for critical AMS blocks (IFXA)
Simulation & characterization activities:
– variability-tolerant low noise / low emission circuits (TMPO)
– Calibrate timing analysis flow (NXP)
– Robust parallel computing architectures by design of demonstrator like
microcontrollers and realize VHDL model (THL)
MODERN General Meetings
Catania, Nov. 9 & 10, 2010
CONFIDENTIAL 1
Task 5.2: Demonstrator design, implementation and
characterization
Review
MODERN General Meetings
Catania, Nov. 9 & 10, 2010
CONFIDENTIAL 2
Task 5.2: Demonstrator design, implementation and
characterization
Purpose of demonstrators (to be aligned during WP5 meeting)
Test-chip activities:
– (UPC)  demonstrate on-chip sensors, level shifters, prove benefits of
circuits with regular layout, digital and RF M&C? (T4.1, T4.4, T3.3)
– (TUGI)  develop benchmark circuits and validate aging models (T2.5)
– (NXP)  verify full-chip substrate analysis (T3.4?)
– (LETI)  verify AVFS (T3.3 timing errors, WP4control), full demo chip
– (IFXA)  verify M&C concepts  T3.3, provide recovery/aging variations
data  T3.3
Simulation & characterization activities:
– (TMPO)  verify variability tolerant low-noise / low-electromagneticemission delay-insensitive asynchronous circuits  WP4
– (NXP)  Calibrate timing analysis flow ???
– (THL)  verify fault tolerant multi-core chip  WP4
MODERN General Meetings
Catania, Nov. 9 & 10, 2010
CONFIDENTIAL 3
Task 5.2: Demonstrator design, implementation and
characterization
Innovative aspects of demonstrators
(to be clarified during WP5 meeting)
Test-chip activities:
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(UPC) 
(TUGI) 
(NXP) 
(LETI) 
(IFXA)  innovative M&C concepts (T3.3), novel aging test and
characterization methods
Simulation & characterization activities:
– (TMPO)  variability tolerant circuits?
– (NXP) 
– (THL) 
MODERN General Meetings
Catania, Nov. 9 & 10, 2010
CONFIDENTIAL 4
Task 5.2: Demonstrator design, implementation and
characterization  Deliverables
Deliverables:
R: Basic concept verification of noise, compensation, test chip
architectures (NXP, IFXA)  M12 (03/2010)  approved
R: Test chip simulation results, topology, implementation and
evaluation strategy, VHDL models; IP block design and layout for the
different technologies CMOS (digital AMS&RF), SOI, etc. and
technology nodes
(TMPO, NXP, IFXA, UPC,THL, LETI, TUGI)  M27 (06/2011)
R: test chip characterization (evaluation to show effectiveness of PVT
circuitry, of basic processing circuits implemented with regular
layouts,), calibration of PV robust analysis flows
(TMPO, UPC, NXP, IFXA, LETI, TUGI)  M36 (03/2012)
MODERN General Meetings
Catania, Nov. 9 & 10, 2010
CONFIDENTIAL 5
MODERN. WP5 Status - UPC
MODERN General meeting
Catania
November 9th, 2010
UPC in relation with T5.2
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Several UPC tasks will produce output susceptible to be a
demonstrator chip
T3.3 PV-aware design
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T4.1: Variability-aware design
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Highly tolerant dgital design
monitor & control of RF
D4.1.2 “Tape-out of prototype on-chip sensors and level shifter
circuits for (self-) adaptive design.”
T4.4: Design of regular architectures for high
manufacturability and yield
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D4.4.2 “Tape-out of a chip based on regular transistor arrays.”
T3.3 – Tolerant redundant circuits:
Turtle logic
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Described in D3.3.1 (M12)
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Signal redundancy in all nodes
Inherently robust against logic discrepancies in complementary signals
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In sequential circuits, state transition stopped when there is a discrepancy
Current status:
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Initially inspired in probabilistic logic
redundant signal sequential architecture already defined
Application example designed at gate level: multiplier 4x4
Next steps:
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Gate-level simulation and evaluation (D3.3.2)
Physical design to evaluate area, timing, power (D3.3.3)
T3.3 - PV monitor and tolerance
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Purpose: design and implement a RF frontSUPPLY
end tolerant to PVT variations, under the
SUPPLY
COMPENSATION
constraint of low-power consumption .
COMPENSATION
RF front-end with a Low Noise Amplifier,
Mixers and auxiliary circuitry for PVT
variations detection and compensation (bias
circuits, detectors, control circuitry, control
loops).
THERMAL
Thermal monitoring will be also considered
as innovative detection technique of PVT COMPENSATION
variations, integrating on chip a differential
temperature sensor.
Status:
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Preliminary block diagram of the proposed
test chip (not indicated possible on-chip
sensors for Built In Test (BIT))
T4. 1 - Monitor and adaptation
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ABB and AVS demonstration to control leakage or delay
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Leakage depends both on VDD and VBS
Delay depends especially on VDD
Current status:
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Evaluation of type of sensors
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In terms of design complexity and parameter yield to improve
Relation/Potential collaboration with LETI
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Sensors based on delay
At schematic/circuit only (different target technology)
Upcoming meeting to define collaboration and excahnge
information
T4.4 - VCTA application for
variation impact of regularity
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Design of Voltage Controlled Delay Line
(VCDL) and DLL
T4.4 - Jitter and mismatch
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Jitter in DLL dependent on mismatch
Sources for mismatch
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Random dopant fluctuations, Interface roughness,
etc.
Lithography interactions between neighboring
patterns
Regular design expected to present smaller
jitter
T4.4 - Experiment proposal
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Design regular (VCTA) and irregular layouts of DLL
If size of transistors is large enough, mismatch
dominated by neighborhood effects
Design several versions with different transistor
sizing
The relative importance of regularity vs random
mismatch will be obtained
D4.4.2: Tape-out of chip based on regular transistor
arrays (M30)
BACK
Summary UPC
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Designs that are well on-track
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Designs that need extra effort
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RF monitoring and compensation (T3.3)
VCTA regular impact experiment (T4.4)
Digital PV-aware (T4.1)
Turtle logic (T3.3)
At this point in time fully confident they can be part of T5.2
Remarks/Questions
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Technology: ST 65nm
Use of CMP reserved budget; which conditions? One chip?
submission date limit?
Motivation & Technology
Task 5.2 - TUG
The overall motivation is to verify physical reliability models including
process variability reflecting the performance of MOS transistors over
lifetime resulting from WP2.
The goal of Task 5.2. is to determine demonstrator circuits sensitive to
the observed degradation effect in order to allow the benchmark of
different aging model development approaches.
Technology:
The entire work is based on austriamicrosystems AG HVCMOS
technology.
MODERN General Meetings
Catania, Nov. 9 & 10, 2010
CONFIDENTIAL 15
Status of Work
Task 5.2 - TUG
Verification of simple Isub based
analytical model
I sub
P  C1 
W
C2
tn
in order to support the validation of
possible benchmark circuits by
including the models into a
reliability simulator.
Elaborate approaches to incorporate the PV into the models.
Close cooperation with TUV which is working on physical PV aware
reliability models based on TCAD and measurement results.
MODERN General Meetings
Catania, Nov. 9 & 10, 2010
CONFIDENTIAL 16
Principle of Reliability Simulator
Task 5.2 - TUG
The principle of the reliability simulation is to represent the device
degradation at different points in time (e.g. after 10 years) by
updating specific SPICE parameters.
The SPICE deck is updated via a dynamic
link between the analog simulator and the
reliability simulator.
MODERN General Meetings
Catania, Nov. 9 & 10, 2010
CONFIDENTIAL 17
BACK
Outlook
Task 5.2 - TUG
Design and fabrication of benchmark structures.
Validation of proposed benchmark cases.
Outstanding deliverables:
– D5.2.2 – M27
– D5.2.3 – M36
SPECIFY
BENCHMARKS
PRIMARY
SIMULATION,
DESIGN AND
LAYOUT
FABRICATION
OF
BENCHMARK
STRUCTURES
VERIFICATION:
BENCHMARK CASES vs. MEASUREMENTS
STRESS
CASE_1
CASE_2
CASE_3
……….….
CASE_N
Benchmark Cases
Benchmark
Structures
Rel. Simulator
Rel. Simulator
Hu derivative
Structure 1
TUV
analytical
model
MINIMOS-NT
Reliability
WC models
NO
DO MEASUREMENTS
AGREE WITH THE RESULTS FROM
SIMULATION?
hierarchically structured
☺/X
FIND OUT
WHY
Structure 2
Structure 2
Structure 4
etc.
MODERN General Meetings
Catania, Nov. 9 & 10, 2010
CONFIDENTIAL 18
YES
BENCHMARK
CASE
OK
Substrate activities for Modern Task 3.4
Sergei Kapora
29 October 2010
Neptune 314 for substrate noise studies
Developed de-embedding scheme
to remove contribution of IO coupling
8 digital IPs
with different isolation approaches
Correlation of de-embedded measurement
results with 3rd-party EDA tool for full-chip
substrate noise analysis
CONFIDENTIAL
20
2010
Neptune 5 test chip specs
isolation
Aggressor
(IO or digital)
isolation
propagation
Victim
(FM LNA)
Current floor plan proposal
Neptune 5
PCB
Spectrum analyzer
Victim 1
analog pads
Spectrum of the output of FM buffer
with and without digital noise present in the system
Victim 5
Victim 6
Victim 7
Victim
settings
Victim 2
Shift
register 1
Shift
register 3
Shift
register 2
Shift
register 4
Digital pads
Control equipment
Digital pattern generator
analog pads
Victim 3
Victim 4
Aggressor
settings
Digital pads
CONFIDENTIAL
21
2010
Substrate extraction flow in SOI
Layout
LVS
Rules
BACK
Schematic
LVS
Internal
Database
QRC
Rules
QRC
Substrate
Tech File
Extracted View
Substrate
Abstract View
Reduction
Circuit simulation
Disturbed output of the bandgap due to
noise propagation through the substrate
*functionality in red is
added to the standard flow
CONFIDENTIAL
22
2010