Transcript MODERN presentation template

Task 5.2: Demonstrator design, implementation and
characterization
Objectives: develop and implement demonstrator chips related to the
major activities carried on the other work-packages
Activities as described in Technical Annex:
Test-chip activities:
–
–
–
–
–
Level shifter circuits, basic circuits implemented with regular layout (UPC)
PV aware and lifetime-critical circuits (TUGI)
Substrate noise (NXP)
PV aware monitors/controls for self-timed logic (LETI)
compensation schemes for critical AMS blocks (IFXA)
Simulation & characterization activities:
– variability-tolerant low noise / low emission circuits (TMPO)
– Calibrate timing analysis flow (NXP)
– Robust parallel computing architectures by design of demonstrator like
microcontrollers and realize VHDL model (THL)
MODERN General Meetings
Catania, Nov. 9 & 10, 2010
CONFIDENTIAL 1
Task 5.2: Demonstrator design, implementation and
characterization
Review
MODERN General Meetings
Catania, Nov. 9 & 10, 2010
CONFIDENTIAL 2
Task 5.2: Demonstrator design, implementation and
characterization
Purpose of demonstrators (to be aligned during WP5 meeting)
Test-chip activities:
– (UPC)  demonstrate on-chip sensors, level shifters, prove benefits of
circuits with regular layout, digital and RF M&C? (T4.1, T4.4, T3.3)
– (TUGI)  develop benchmark circuits and validate aging models (T2.5)
– (NXP)  verify full-chip substrate analysis (T3.4?)
– (LETI)  verify AVFS (T3.3 timing errors, WP4control), full demo chip
– (IFXA)  verify M&C concepts  T3.3, provide recovery/aging variations
data  T3.3
Simulation & characterization activities:
– (TMPO)  verify variability tolerant low-noise / low-electromagneticemission delay-insensitive asynchronous circuits  WP4
– (NXP)  Calibrate timing analysis flow ???
– (THL)  verify fault tolerant multi-core chip  WP4
MODERN General Meetings
Catania, Nov. 9 & 10, 2010
CONFIDENTIAL 3
Task 5.2: Demonstrator design, implementation and
characterization
Innovative aspects of demonstrators
(to be clarified during WP5 meeting)
Test-chip activities:
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–
–
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(UPC) 
(TUGI) 
(NXP) 
(LETI) 
(IFXA)  innovative M&C concepts (T3.3), novel aging test and
characterization methods
Simulation & characterization activities:
– (TMPO)  variability tolerant circuits?
– (NXP) 
– (THL) 
MODERN General Meetings
Catania, Nov. 9 & 10, 2010
CONFIDENTIAL 4
Task 5.2: Demonstrator design, implementation and
characterization  Deliverables
Deliverables:
R: Basic concept verification of noise, compensation, test chip
architectures (NXP, IFXA)  M12 (03/2010)  approved
R: Test chip simulation results, topology, implementation and
evaluation strategy, VHDL models; IP block design and layout for the
different technologies CMOS (digital AMS&RF), SOI, etc. and
technology nodes
(TMPO, NXP, IFXA, UPC,THL, LETI, TUGI)  M27 (06/2011)
R: test chip characterization (evaluation to show effectiveness of PVT
circuitry, of basic processing circuits implemented with regular
layouts,), calibration of PV robust analysis flows
(TMPO, UPC, NXP, IFXA, LETI, TUGI)  M36 (03/2012)
MODERN General Meetings
Catania, Nov. 9 & 10, 2010
CONFIDENTIAL 5
MODERN. WP5 Status - UPC
MODERN General meeting
Catania
November 9th, 2010
UPC in relation with T5.2
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Several UPC tasks will produce output susceptible to be a
demonstrator chip
T3.3 PV-aware design
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T4.1: Variability-aware design
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Highly tolerant dgital design
monitor & control of RF
D4.1.2 “Tape-out of prototype on-chip sensors and level shifter
circuits for (self-) adaptive design.”
T4.4: Design of regular architectures for high
manufacturability and yield
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D4.4.2 “Tape-out of a chip based on regular transistor arrays.”
T3.3 – Tolerant redundant circuits:
Turtle logic
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Described in D3.3.1 (M12)
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Signal redundancy in all nodes
Inherently robust against logic discrepancies in complementary signals
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In sequential circuits, state transition stopped when there is a discrepancy
Current status:
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Initially inspired in probabilistic logic
redundant signal sequential architecture already defined
Application example designed at gate level: multiplier 4x4
Next steps:
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Gate-level simulation and evaluation (D3.3.2)
Physical design to evaluate area, timing, power (D3.3.3)
T3.3 - PV monitor and tolerance
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
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Purpose: design and implement a RF frontSUPPLY
end tolerant to PVT variations, under the
SUPPLY
COMPENSATION
constraint of low-power consumption .
COMPENSATION
RF front-end with a Low Noise Amplifier,
Mixers and auxiliary circuitry for PVT
variations detection and compensation (bias
circuits, detectors, control circuitry, control
loops).
THERMAL
Thermal monitoring will be also considered
as innovative detection technique of PVT COMPENSATION
variations, integrating on chip a differential
temperature sensor.
Status:
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Preliminary block diagram of the proposed
test chip (not indicated possible on-chip
sensors for Built In Test (BIT))
T4. 1 - Monitor and adaptation
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ABB and AVS demonstration to control leakage or delay
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Leakage depends both on VDD and VBS
Delay depends especially on VDD
Current status:
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Evaluation of type of sensors
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In terms of design complexity and parameter yield to improve
Relation/Potential collaboration with LETI
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Sensors based on delay
At schematic/circuit only (different target technology)
Upcoming meeting to define collaboration and excahnge
information
T4.4 - VCTA application for
variation impact of regularity
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Design of Voltage Controlled Delay Line
(VCDL) and DLL
T4.4 - Jitter and mismatch
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Jitter in DLL dependent on mismatch
Sources for mismatch
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Random dopant fluctuations, Interface roughness,
etc.
Lithography interactions between neighboring
patterns
Regular design expected to present smaller
jitter
T4.4 - Experiment proposal
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Design regular (VCTA) and irregular layouts of DLL
If size of transistors is large enough, mismatch
dominated by neighborhood effects
Design several versions with different transistor
sizing
The relative importance of regularity vs random
mismatch will be obtained
D4.4.2: Tape-out of chip based on regular transistor
arrays (M30)
BACK
Summary UPC
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Designs that are well on-track
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Designs that need extra effort
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RF monitoring and compensation (T3.3)
VCTA regular impact experiment (T4.4)
Digital PV-aware (T4.1)
Turtle logic (T3.3)
At this point in time fully confident they can be part of T5.2
Remarks/Questions
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Technology: ST 65nm
Use of CMP reserved budget; which conditions? One chip?
submission date limit?
Motivation & Technology
Task 5.2 - TUG
The overall motivation is to verify physical reliability models including
process variability reflecting the performance of MOS transistors over
lifetime resulting from WP2.
The goal of Task 5.2. is to determine demonstrator circuits sensitive to
the observed degradation effect in order to allow the benchmark of
different aging model development approaches.
Technology:
The entire work is based on austriamicrosystems AG HVCMOS
technology.
MODERN General Meetings
Catania, Nov. 9 & 10, 2010
CONFIDENTIAL 15
Status of Work
Task 5.2 - TUG
Verification of simple Isub based
analytical model
I sub
P  C1 
W
C2
tn
in order to support the validation of
possible benchmark circuits by
including the models into a
reliability simulator.
Elaborate approaches to incorporate the PV into the models.
Close cooperation with TUV which is working on physical PV aware
reliability models based on TCAD and measurement results.
MODERN General Meetings
Catania, Nov. 9 & 10, 2010
CONFIDENTIAL 16
Principle of Reliability Simulator
Task 5.2 - TUG
The principle of the reliability simulation is to represent the device
degradation at different points in time (e.g. after 10 years) by
updating specific SPICE parameters.
The SPICE deck is updated via a dynamic
link between the analog simulator and the
reliability simulator.
MODERN General Meetings
Catania, Nov. 9 & 10, 2010
CONFIDENTIAL 17
BACK
Outlook
Task 5.2 - TUG
Design and fabrication of benchmark structures.
Validation of proposed benchmark cases.
Outstanding deliverables:
– D5.2.2 – M27
– D5.2.3 – M36
SPECIFY
BENCHMARKS
PRIMARY
SIMULATION,
DESIGN AND
LAYOUT
FABRICATION
OF
BENCHMARK
STRUCTURES
VERIFICATION:
BENCHMARK CASES vs. MEASUREMENTS
STRESS
CASE_1
CASE_2
CASE_3
……….….
CASE_N
Benchmark Cases
Benchmark
Structures
Rel. Simulator
Rel. Simulator
Hu derivative
Structure 1
TUV
analytical
model
MINIMOS-NT
Reliability
WC models
NO
DO MEASUREMENTS
AGREE WITH THE RESULTS FROM
SIMULATION?
hierarchically structured
☺/X
FIND OUT
WHY
Structure 2
Structure 2
Structure 4
etc.
MODERN General Meetings
Catania, Nov. 9 & 10, 2010
CONFIDENTIAL 18
YES
BENCHMARK
CASE
OK
Substrate activities for Modern Task 3.4
Sergei Kapora
29 October 2010
Neptune 314 for substrate noise studies
Developed de-embedding scheme
to remove contribution of IO coupling
8 digital IPs
with different isolation approaches
Correlation of de-embedded measurement
results with 3rd-party EDA tool for full-chip
substrate noise analysis
CONFIDENTIAL
20
2010
Neptune 5 test chip specs
isolation
Aggressor
(IO or digital)
isolation
propagation
Victim
(FM LNA)
Current floor plan proposal
Neptune 5
PCB
Spectrum analyzer
Victim 1
analog pads
Spectrum of the output of FM buffer
with and without digital noise present in the system
Victim 5
Victim 6
Victim 7
Victim
settings
Victim 2
Shift
register 1
Shift
register 3
Shift
register 2
Shift
register 4
Digital pads
Control equipment
Digital pattern generator
analog pads
Victim 3
Victim 4
Aggressor
settings
Digital pads
CONFIDENTIAL
21
2010
Substrate extraction flow in SOI
Layout
LVS
Rules
BACK
Schematic
LVS
Internal
Database
QRC
Rules
QRC
Substrate
Tech File
Extracted View
Substrate
Abstract View
Reduction
Circuit simulation
Disturbed output of the bandgap due to
noise propagation through the substrate
*functionality in red is
added to the standard flow
CONFIDENTIAL
22
2010
LETI MODERN Contribution to WP5
Contribution to WP5.2: Demonstrator : design,
implementation and characterization
Status :
– Design of a full chip in 32 nm : LoCoMoTIV
– Full AVFS architecture
– Including WP3 and WP4 IP contributions
– PG tape : December
Deliverables:
– D5.2.2: Test chip simulation results : on track
– D5.2.3 : IP block design and layout : on track
– D5.5.4 : test chip characterization : on track
CONFIDENTIAL
2010
A dynamic adaptive Architecture
4
3,5
Puissance (Consommation)
3
Puissance (Série4)
– Performances improvements: DVFS vs AVFS
200
DVFS
AVFS
180
Puissance (Période min)
2,5
3,4
Puissance (PERIODE MIN MONITORS)
3,2
2
3
160
Decision Maker
Parameter Control
2,8
1,5
140
Same Speed
2,6
1
2,4
Diagnostic
S
120
1,1
1,15
1,2
1,25
2,2
100
1,8
60
1,6
1,4
40
1,2
Same Power
1
20
0,9
0,95
1
1,05
1,1
1,15
1,2
K
K : Actuators
S : Sensors
S
Action
K
S
Puissance (Série4)
K
Digital Block
Puissance (Période min)
1 Power/Frequency domain
Puissance (PERIODE MIN MONITORS)
Period (ns)
80
S
Puissance (Consommation)
Circuit
2
Power (mW)
05
4,5
1,25
Power supply (V)
CONFIDENTIAL
2010
Architecture Overview
A fine grain Local Dynamic Adaptive voltage and frequency
scaling architecture
Diagnostic:
– Process-Voltage-Temperature
– Timing fault detection or prevention (WP3)
RunTime
ANOC
Actuators:
– Based on Vdd-hopping
– Local clock generation using FLL
Power/Variability Control
CVPU
0.9v
0.7v
CVPU
PE
0.9v
0.7v
PE
– Local control with minimum hardware (WP4)
– Global control : high level algorithms
Main HW objective : a minimum hardware based on standard cells
and simple analog macros for flow insertion and maximum efficiency
CONFIDENTIAL
2010
LoCoMoTIV architecture
Local Compensation of Modern Technology Induced Variability
An AVFS GALS approach at fine grain to reach an optimum energetic
point according to PVT variations
ITs
Asynchronous NoC
ITs
WDT
DMA
L2-RAM
4 XP70 µP
Dedicated memory
blocks
V/F Local actuators
Local Controller
CVP : ClockVraiability-Power
M
NI
NI
CVP-U
NI
CVP-U
NI
NI
Memory
Mapped
Peripherals
NI
16KB P-$
16KB P-$
16KB P-$
32-KB TCDM
32-KB TCDM
32-KB TCDM
32-KB TCDM
STxP70-V4
Hopping /
(Rev.
FLL A)
+ ITC
PVT
S
#1
STxP70-V4
Hopping /
(Rev.
FLL A)
+ ITC D-$
PVT
S
#2
STxP70
STxP70
OCE
OCE
OCE
OCE
TMS TCK TDI TDO BI
BO
TMS TCK TDI TDO BI
HWS
M
NI
ANOC
16KB P-$
Timing Fault
Detectors
PVT sensors
S
NI
BO
TMS TCK TDI TDO BI
BO
TMS TCK TDI TDO BI
BO
Debug & Test Unit
CONFIDENTIAL
2010
BACK
LoCoMoTIV flooplan
Fully digital FLL :
Frequency
generation
PVT probes
Hopping transition
and switches :
Voltage genration
PE1
PE0
L2RAM
ANOC
CDMA
PE2
PE3
CONFIDENTIAL
2010
Task 5.2
IFXA  Objective and Outline
Objective: development and verification of monitor & control (M&C)
strategies for AMS&RF circuits to deal with aging/reliability issues and
aging induced parameter variations in nanometer CMOS.
Close link to T3.3 (M&C concept development)
Outline
– Basic aging/reliability assessment  identify sensitivities
• Aging simulations (proof of sim.-concept, model-hardware correlation in T5.2)
• Dedicated test-structures for transient effects and aging-parameter-variations
– Development of M&C concepts  T3.3
– Implementation and verification of M&C concepts
• Silicon based proof of concept
• Concept development for accelerated aging/stress tests  T5.2
• Development of characterization methods (fast transient effects)  T5.2
MODERN General
CONFIDENTIAL
28
2010
Task 5.2
IFXA  Completed and Remaining Activities
Test-chip status:
– TC #1 (32nm CMOS): taped, lab characterization completed
– TC #2 (32nm CMOS): taped, lab characterization on-going
– TC #3 (28nm CMOS): design on-going, tape-out end 2010
Status basic aging/reliability assessment (-> circuit level results)
– Circuit level aging simulation flow proven on TC1 (OpAmps, VCOs)
– Structures for transient effects and aging-variations implemented on TC2
OpAmp: Offset drift
VCO: aging of startup VDD
Static offset
Recovery
MODERN General
CONFIDENTIAL
29
2010
BACK
Task 5.2
IFXA  Completed and Remaining Activities
Status implementation & verification of M&C concepts
– Accelerated aging test-setup proven on TC1 and TC2 (OpAmps, VCOs)
– Fast offset characterization method (transient effects) proven on TC2
– Measurements to be finalized on TC2
•
•
•
•
ADC incl. error correction (static & transient offsets)
Switch degradation monitor circuits
Variations of aging parameters
Novel burn-in concept (to increase robustness and compensate PV)
– Macros to be implemented on TC3
V-Sense
Figure 5: Chip Micrograph
Refbuf
NDEMOS
PDEMOS
ESD
PID
ESD
ESD
ESD
• Switch control circuits to be implemented on TC3
• DCDC test-structures
MODERN General
CONFIDENTIAL
30
2010
Task 3.3
IFXA  Key Results Aging Assessment
Majority of key blocks AMS & RF is inherently robust (“self-regulation”)
Sensitive cases
– Non-linear / asymmetric operation (comparator)
– Full scale driven devices (switches, VCO, …)
Transient effects (recovery) significantly contribute
Variations of aging parameters need to be considered ( T5.2)
Scaling 65nm to 32nm: not absolute values but sensitivities change
OpAmp: Offset drift
VCO: aging of startup VDD
Static offset
Recovery
MODERN General
CONFIDENTIAL
31
2010
Task 3.3
IFXA  Key Results M&C Development
Switches
– Monitor concepts: ring oscillator, current sensing
– Control: “frequency locked loop”, analog control loop
Aging induced offsets
– Avoid offset generation: e.g. chopping (comparator)
– Correction of static & dynamic effects: e.g. error correction by redundancy
– Burn-in: dedicated stress to increase robustness and compensate PV
stress pattern
control voltage
ADC search algorithm incl. redundancy
...
Inv 1
...
Inv 2
Inv n
switch replicas
enable
ref.
switch on-voltage
Phase
Frequency
Detector
MODERN General
Charge
Pump
Loop
Filter
Ringo
Monitor
Frequency
Divider
CONFIDENTIAL
32
2010
Task 3.3
IFXA  Completed and Remaining Activities
Testchip #1 and #2 taped, samples not fully characterized, design of #3
on-going
Basic aging/reliability assessment  almost completed
– Simulations completed, sim.-concept verified (TC1, OpAmps, VCOs)
– Structures for transient effects and aging-variations implemented on TC2
Development of M&C concepts  completed
Implementation and verification of M&C concepts  ongoing
– Accelerated aging test-setup proven on TC1 and TC2
– Fast offset characterization method proven on TC2
– TC2
• Switch monitor circuits
• ADC incl. error correction
– TC3
• Switch control circuits to be implemented on TC3
• DCDC test-structures
• Concept development for accelerated aging/stress tests
MODERN General
CONFIDENTIAL
33
2010
MODERN General
CONFIDENTIAL
34
2010
MODERN General
CONFIDENTIAL
35
2010
BACK
MODERN General
CONFIDENTIAL
36
2010
MODERN
WP5
THALES foreseen activities
10 November 2010
THL activities in MODERN linked to WP5
Up to now we (THL) have had contributions in WP4 to develop a
SystemC simulator of a predictable fault-tolerant multicore chip (based
on the ISD network) with embedded middleware and operating
libraries.
•
•
•
•
•
•
•
developed a processor tile
designed and implemented fault injection scenarios
design the multicore chip with ISD network
implemented a SystemC simulator of the chip
designed and implemented operating libraries, middleware and tools
modified in-house tools to generate parallel code for this architecture
designed, developed and implemented a video detection algorithm on top of
the architecture based on the Viola & Jones face detection (Haar filters).
20 November 2009
Slide 38 of 19
CONFIDENTIAL WP4
Web
2010
Meeti
Architecture (SystemC)
iNoC : Internal Network OCP TL2
Supervisor : TILE 0
CTR
CTR
DMA
DMA
NIM
LMEM
TILE 1
ACC
LMEM
CTR
…
NIM
DMA
TILE N
ACC
LMEM
NIM
ISD HyperCube Network
CTR: ConTRoler
DMA: Direct Memory Access
NIM: Network Interface Module
(Makes network protocol translation)
NUMA
SHMEM
ACC: ACCelerator
LMEM: Local MEMory
SHMEM: SHared MEMory
NUMA: Non Uniform Memory Access
20 November 2009
Slide 39 of 19
CONFIDENTIAL WP4
Web
2010
Meeti
Fault Scenario Definition
Memory faults: a fault occurs randomly in shared data
memory (e.g. wrong value written). A read time, the
memory tells the reading tile that data contains errors. This
reading tile sends a message to the supervisor tile. The
supervisor takes actions to solve the problem.
Tile faults: a processing tile sends periodically a message
to the supervisor tile (watchdog). When it stops doing so,
the supervisor takes actions to solve the problem.
To solve a problem, the supervisor :
–
–
–
–
Stops the processing tiles
Find a new memory mapping and tile mapping.
Configure the network according to that mapping.
Restart the processing tiles
20 November 2009
Slide 40 of 19
CONFIDENTIAL WP4
Web
2010
Meeti
BACK
WP5 foreseen activities and deadlines
WP5: multicore chip FPGA implementation
Supervisor : TILE 0
CTR
DMA
LMEM
– M27: D5.2.2:
• VHDL IPs developed
– supervisor Tile, NIM, SHMEM controler, NoC
• Software developed
NIM
– Tile bootloader, SHMEM test access
– M36: D5.3.3
•
•
•
•
Several Tiles (12 foreseen)
Develop HAL
Reuse Operating Libraries from SystemC
Video detection application.
CONFIDENTIAL
2010