Transcript Document
MODERN ENIAC WP2 Meeting
WP2 Tasks review summary Catania, 2010 Nov. 09-10
Project Review Meeting Catania, Nov.09-10, 2010
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Contents
• WP2 • Task 2.1 to 2.5 summary • Matrix, Gantt chart, relation with other Wps • Action points from meeting
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WP2: Relationship among work packages
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MODERN General Meetings Catania, Nov.
WP2 Objectives
•
Objectives
• Provide a chain of TCAD simulations tools which enable simulation of the impact of process variations and reliability on device level, including compact models and mixed mode device/circuit simulation • Assess the impact of process and device variations for relevant technologies, mainstream planar bulk CMOS down to 45/32nm, new device architectures on bulk & on SOI suitable for 22nm, NVM technologies, and non silicon technologies • Compare simulation results with hardware and calibrate them on hardware to verify PV methodology and to foster physical understanding of major sources of PV in above technologies
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WP2 Key Figures
• 5 Tasks/18 deliverables (reports): – Process (2) & device (6) simulation – Electrical characterization (4) & Reliability(3) – Compact modeling (3) – Covering both Tools/Methodology improvements and Application results • Wide spectrum of technologies & devices applications – 45nm: planar Mosfet – 32nm: planar Mosfet, FinFet – 22nm: FD SOI Mosfet – State-of-art NVM – Discrete Power Device, SiC, GaN/AlGaN – HV CMOS •
TOTAL EFFORT: 638.6 PM =53.22 PY
•
Reference: MODERN Rev2.1.7 project description
Project Review Meeting Catania, Nov.09-10, 2010
Technologi es
Task
HVMOS Planar CMOS NVM FDSOI
65nm 45nm 32nm 41nm WP2 meeting Domain overview per task and partner
Process simulation
2.1
Device simulation
2.2
Electrical Charact.
2.3
Reliability
2.4
Compact Modeling
2.5
AMS TUW UNGL POLI SNPS (STF2) UNGL POLI (STF2) UNET NMX SNPS IMEP (STF2) IMEP STF2 IMEP STF2 UNET NMX LETI IMEP AMS TUW UNCA UNGL UNET (NMX) AMS TUW UNGL POLI STF2 NXP UNGL UNET NMX LETI
Finfets, MUG, GAA SiC Power MOS AlGaN-GaN HEMT
STI STI STF2 NXP STI STI IMEP STI STI PV aware tools and methods are of common interest; they are developped and applied to a wide spectrum of technologies (Project book rev2 v2.4.1).
Significant communalities of technology targets, except different ones for Process and Device simulation. (not funded) Catania, Nov. 9 & 10, 2010
WP2 Task Definition and Contributors
WP2 Process/Device to Compact Modeling Contributors T2.1
PV aware process simulation ST-I, AMS, TUW T2.2
PV aware device simulation UNGL, IMEP, UNET, NMX, POLI, STF2, ST-I, SNPS T2.3
Electrical characterization of PV, software (TCAD) / hardware comparison & calibration NXP, AMS, IMEP, UNET, LETI, NMX, STF2, ST-I T2.4
T2.5
Correlation between PV and reliability, reliability modeling PV aware compact modeling AMS, IMEP, UNET, TUW, UNCA, UNGL UNET, AMS, LETI, NMX, NXP, POLI, STF2, ST-I, UNG Project Review Meeting Catania, Nov.09-10, 2010
WP2 T2.1
T2.2
T2.3
T2.4
T2.5
STF2
WP2 Task Leaders
ST-I UNGL NXP AMS UNET [email protected]
Contents
• WP2 introduction • Task 2.1 to 2.5 summary • Matrix, Gantt chart, relation with other Wps • Action points from meeting
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MODERN General Meeting
Task 2.1 summary
Catania, Nov. 9-10 2010
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Process simulation: T2.1 Deliverables
Ref D2.1.1
D2.1.2
Deliverable/ Contributors First process simulation including treatment of PV for Discrete Power Device, HV-CMOS, SiC, GaN/AlGaN technologies, interfaced to commercial TCAD tools (
ST-I, AMS, TUW
) Due date M15 Done Enhanced process simulation including treatment of PV for Discrete Power Device, HV-CMOS, SiC, GaN/AlGaN technologies, interfaced to commercial TCAD tools (
ST-I, AMS, TUW
) M27 Task Leader:
Process flow Virtual device High Level factory Specific process conditions Technology transferred to FAB2 using PCM
FAB1 FAB2 PCM
Mask Layout
Process Compact model derived from TCAD 12 PCM
MODERN General Meetings Catania, Nov.
PCM approach
EHD5 SEMICELL
Synopsys platform: Sentaurus and PCM Studio
SENTAURUS WORKBENCH
Simulation of Power-Mos semi cell with the nominal values of the process input parameters
D OE PCM PCM STUDIO
Parameter screening to identify the process parameters that have an important impact on target electrical parameters.
Parameterized simulation setup ( DOE ) generating several simulation runs.
Device simulations of breakdown and I-V characteristic for each experiment.
Extraction of RSM model using PCM Studio.
of device characteristics as function of process parameters
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MODERN General Meetings Catania, Nov.
• Process Flow
Process Variation at AMS - TUW Parameters Sentaurus Work Bench Interface between commercial Synopsys Process Simulator and Minimos Device Simulator Parameter Extraction Correlation Minimos
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MODERN General Meetings Catania, Nov.
WP2 T2.1 action items
• Task 2.1: Process simulation –
D2.1.2 (M27): « Enhanced process simulation including treatment of PV for Discrete Power Device, HV-CMOS, SiC, GaN/AlGaN technologies, interfaced to commercial TCAD tools (ST-I, AMS, TUW) »
AI (STI, AMS, M27): HVMOS and AsGaN-SiC device sensitivity analysis to Process variations to be validated on HW data available from D2.3.2
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MODERN General Meeting
Task 2.2 summary
Catania, Nov. 9-10 2010
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Ref D2.2.1
D2.2.2
D2.2.3
Device Simulation: T2.2 Deliverables
Deliverable/ Contributors Assessment of state-of-the-art TCAD methodology and usability concerning PV for industrial purposes including identification of current deficiencies of tools (
UNGL
) Device simulation analysis of dominant variability sources in 45nm planar bulk CMOS technologies, and Discrete Power Device,SiC, GaN/AlGaN technologies. Prototype implementation of the treatment of individual dopants and traps in the device modeling tools (
UNGL, UNET, NXP, ST-I, SNPS
) Device simulation analysis of dominant variability sources in state of-the-art Non Volatile-Memory technologies (
UNET, UNGL, NMX, SNPS
) D2.2.4
D2.2.5
D2.2.6
Forecast of the magnitude of statistical variability in 32nm planar bulk CMOS devices via device simulation (
UNGL, IMEP, UNET
). Efficient compact model extraction procedures for modeling process variations and device fluctuations (
NXP, UNET, POLI
) Application of mixed-mode device-circuit simulations for the analysis of the impact of fluctuations (
UNET
) TCAD based assessment of PV effects of potential 22nm device architectures (
UNGL
) Sensitivity analysis of Non Volatile Memory device performance as a function of individual trap position (
NMX,UNET)
Toolbox (methodologies, models, tools) to make dominant variability effects accessible to industrial usage of TCAD Outlook to 16nm device architecture robustness using MASTAR (
UNGL, STF2
) Task Leader:
Due date M6 M12 M18 M24 M27 M36
T2.2.2 Overview
V D =50mV V D =1.0V
V D =50mV V D =1.0V
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T2.2.2 Overview
(Synopsys) (UNET Università di Udine)
T2.2.2 Overview
(UNET Università di Bologna)
RDD (Glasgow) RDD (Numonyx) RDF (Synopsys)
T2.2.3 Overview
1.15
1.025
σV T [mV] 141 146 137 RDD LER LWR OTF PSG ITC
T2.2.3 Overview
Flat AA &FG Rounded AA & FG RDD (Glasgow) RDD (Numonyx) RDD+Rounded (Numonyx)
1.15
1.19
σV T [mV] 141 146 161 Uniform All Sources
σV T [mV] Calc. σV T [mV] 1.32
169 166.3
T2.2 action items
• Task 2.2: Device simulation –
D2.2.4 (M24): « Forecast of the magnitude of statistical variability in 32nm planar bulk CMOS devices via device simulation (UNGL, IMEP, UNET
)” AI (STF2, Nov 2010): to provide TCAD decks. 5-way NDA between UNGL UNET-SNPS-POLI-ST applies.
– D2.2.5 (M27):
« TCAD based assessment of PV effects of potential 22nm device architectures (UNGL )”
=> AI (WP leader, Nov 2010): contact LETI on demonstrator devices (FDSOI, Finfets?,…) and associated templates. Backup template devices already available at UNGL. Need decision latest Feb 2011.
– D2.2.6 (M36):
« Sensitivity analysis of Non Volatile Memory device performance as a function of individual trap position (NMX,UNET) . Toolbox (methodologies, models, tools) to make dominant variability effects accessible to industrial usage of TCAD. Outlook to 16nm device architecture robustness using MASTAR (UNGL, STF2 )”
=> AI(T2.2 Leader): Contact SNPS if they intend to contribute to toolbox
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MODERN General Meeting
Task 2.3 summary
Catania, Nov. 9-10 2010
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Ref D2.3.1
D2.3.2
D2.3.3
D2.3.4
Electrical Characterization: T2.3 Deliverables
Deliverable/ Contributors Characterization of the influence of variability sources in planar bulk CMOS devices down to 45nm (
STF2, IMEP, UNET, NXP
) Experimental characterization of Non-Volatile- Memory devices in the presence of PV (
NMX, UNET
) Parametric mismatch fluctuation effects in 32 nm FinFETs, first PV results on 22nm FDSOI MOSFETS (
LETI, NXP
) Characterization of major sources of PV in SiC technologies/devices, and AlGaN/GaN HEMT devices (
ST-I)
Report on 1/f noise dispersion behavior in 45nm bulk CMOS (
NXP
) Identification of most relevant process variations in planar bulk CMOS devices down to 32nm, parameter fluctuation effects based on hardware (
STF2, NXP, UNET, AMS
) Sources for PV in new device architectures, suitable for 22nm CMOS; major deltas in comparison to standard planar bulk CMOS (
IMEP, NXP, LETI
) Report on high-level models, both analytical and graphical , for PV of Non-Volatile Memory devices (
NMX
) Report on 1/f noise dispersion behavior in 32 nm planar bulk CMOS (
NXP
) Due date M12 M18 M30 M36 Task Leader:
Project Review Meeting Crolles, June 22, 2009
Task T2.3 D2.3.1:
Characterization of the influence of variability sources in planar bulk CMOS devices down to 45nm (ST, IMEP, UNGL)
W (µm) 0.12
1 5 0.15
0.15
0.12
1 1 0.12
0.12
L (µm) 5 0.04
0.04
0.04
1 1 0.05
0.08
0.05
0.2
Example of 45nm Nmos with pocket implants: Conventional DOE and electrical characterization technique Geometry scaling on transistor area impacted by Lateral doping gradient Compact analytical model developed with 3 channel regions wi/wo pockets explains qualitative trend of Lscaling for VT mismatch UNGL 3D simulation (D2.2.2) in line with experiments 12 10 8 6 4 2 0 0.01
MODERN 1st 26 June 30, 2010 0.1
Ideal scaling law 1 10
L (µm)
Task T2.3 D2.3.1:
Experimental characterization of NVM devices (41nm, xGbits )in the presence of PV (NMX)
Neutral device scaling: Local random variations for W,L, Oxide, Interpoly dielectric, RDD fluctuations (top) Local systematic: Cell to cell interference (bottom) After programming: Local random Local systematic VT Shift induced by neighbouring cells (top), or string series resistances (bottom) MODERN 1st 27 June 30, 2010
Task T2.3 D2.3.1:
First PV results on 22nm FDSOI MOSFETS (Leti, NXP)
P10 - HfSiO 2,3nm / TiN PVD 5nm - CESL neutre
60 50 40 30 20
AVt=1.4mV.µm AVt=1.2mV.µm pFETs
V T mismatch (@ 1V Vd) for FDSOI nFETs and pFETs. High-k/metal gate stack. STI isolation. T Si =6nm, L min =30nm, W min =80nm
10
nFETs
0 0 5 10
1/sqrt(LxW) (µm)
15 20 50 A VT =1.45mV.µm 40 nMOS 30 pMOS
V T mismatch for UT2B vs thick BOX MOSFETs. High-k/metal gate stack. STI isolation. T Si =8nm.
20 10 0 0 5 Open: Thick BOX Closed: UT2B 10 15 1/sqrt(WxL) (µm) 20 25 Record matching performance for FDSOI (top) VT matching not degraded by UTBOX vs Thick box substrates (bottom) MODERN 1st 28 June 30, 2010
Task T2.3 D2.3.1:
Parametric mismatch fluctuation effects in 32 nm SOI FinFETs (NXP, LETI)
GIDL VT Rseries
Mismatch signature analysis on FinFET population. W Fin =10 nm, L g =100 nm a: collection of 96 (V
DS
=1.2 V) transfer curves for transistor 1 (I D1 ) of each pair. b: ΔI D /I D vs. V GS for all pairs of the population (ΔI c: mismatch signature: σ_ΔI D /I D D /I D = 200 x (I D1 -I D2 )/(I D1 +I D2 ) ). (red triangles) and mismatch auto correlation (black X’s) vs. V GS .
a: Drain access resistance improvement from 700 to 280 Ωμm . θ vs. β slope corresponds to R SD . b: V T mismatch fluctuations vs. area. A ΔVT increases from 1.9 mVμm (solid line) to 2.4 mVμm (dashed line) with 10 18 channel doping
Powerful Mismatch signature analysis concept demonstrated A ΔVT down to 2 mVμm range demonstrated MODERN 1st 29 June 30, 2010
T2.3 action items
• Task 2.3: Characterization and simulation verification – D2.3.2 (M18)/D2.3.4 (M36):
« 1/f noise dispersion”
=> AI (WP leader): Ask NXP about plan to develop compact model within Modern – D2.3.4: (M36)
« Report on high-level models, both analytical and graphical , for PV of in Non-Volatile-Memory devices (NMX )”
AI change title: « Report on high-level models, both analytical and graphical , for PV of devices in Non-Volatile-Memory technologies (
NMX
)”
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MODERN General Meeting
Task 2.4 summary
Catania, Nov. 9-10 2010
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Ref D2.4.1
D2.4.2
D2.4.3
Reliability: T2.4 Deliverables
Deliverable/ Contributors Specification of considered degradation effects, modeling approaches and device parameters (
UNGL, TUW
) Due date M6 (Done) Hardware results of aging measurements available, on planar bulk CMOS technologies (
AMS, TUW, UNET, UNCA
) M24 Implementation of statistical degradation effects into aging models, hardware calibration of degradation effects (
IMEP, AMS, TUW, UNGL, UNET, UNCA
) M33 Task Leader:
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MODERN General Meetings Catania, Nov. 9 & 10, 2010
WP2/ Task 2.4 contributions
Effects -> Technologies
HV mos 65nm cmos 45nm cmos
HCI
AMS TUW UNCA (NXP) UNGL UNCA (NXP) NVM Thin Si
NBTI
AMS TUW UNGL
TDDB RTN/Trapping/ De-trapping SBD/BD
UNGL UNET (NMX) IMEP AI(all, end 2010): WP2 and per Task work matrix completion
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MODERN General Meetings Catania, Nov. 9 & 10, 2010
T2.4 Review Summary
• Activity done so far, with highlights on technical results, and dissemination D2.4.1 deliverable: done.
- NBTI and HC data (0.35 µm LV-CMOS & HV-CMOS): available for TCAD simulations.
- Initial physics-based analytical model for NBTI to implement in circuit simulator.
- Time dependent modeling of degradation for NBTI & HC.
• Plan for D2.4.2 deliverable (M24): - TCAD reliability simulations focused on HV-CMOS.
- Hot-Carrier lifetime model for HV-CMOS by modified Hu-model.
- Threshold Voltage Mismatch Induced by Hot-Carrier in 65 and 45 nm Technology Node.
• Plan for D2.4.3 deliverable (M33): - Statistical compact Models will be extracted at different levels of NBTI and PBTI.
- Time dependence of the statistical compact models will be provided based on NBTI and PBTI models of trap charge as a function of time.
- Analytical NBTI and HC model developments for LV- & HV-CMOS.
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NBTI & Hot-Carrier Activities (1)
• Extraction of capture/emission time maps
– Compact modeling using RC circuits
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MODERN General Meetings Catania, Nov. 9 & 10, 2010
NBTI & Hot-Carrier Activities(2)
• • SE-mechanism: • ME-mechanism:
I
dlin _
N it
,
SE N it
,
ME
N N
0 0 1 1
x
max 1
x
min
x
max
e x
min
tI
(
x
)
dx
, exp(
ME t
) 1 / 2 degradation represented by the compact model
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MODERN General Meetings Catania, Nov. 9 & 10, 2010
Threshold Voltage Mismatch Induced by Hot-Carrier in 65 and 45 nm Technology Node 37
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Lifetime Models for High-Voltage NMOS
V d : 35V, 40V, 45V, 50V, 55V Modified Model of Hu:
I D
C
g
I B I D
g
blue data points: -40 ° C red data points: +25 ° C
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MODERN General Meetings Catania, Nov. 9 & 10, 2010
WP2 action items
• Task 2.4: Statistical Reliability – D2.4.2 (M24): «
Hardware results of aging measurements available, on planar bulk CMOS technologies (AMS, TUW, UNET, UNCA )”
=> AI (UNCA, working with NXP): addition of sub-Vt slope to Vt figure for HCI effects – D2.4.3 (M33) «
Implementation of statistical degradation effects into aging models, hardware calibration of degradation effects (IMEP, AMS,
TUW, UNGL, UNET, UNCA
)”
AI (AMS, TUW): Implementation of process variations in NBTI/HCI degradation compact models for HV devices remains challenging task (physics complexity); nevertheless achievable with some approximations to physics AI (UNGL): UNGL to clarify contents of contribution to NBTI/HCI compact models
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MODERN General Meeting
Task 2.5 summary
Catania, Nov. 9-10 2010
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Compact Modeling: T2.5 Deliverables
Ref D2.5.1
D2.5.2
D2.5.3
Deliverable/ Contributors PV-aware circuit-level models for standard CMOS technologies (down to 45nm) (
UNGL, UNET, NXP, POLI, ST-I, STF2
) , and Non-Volatile-Memory technologies (
NMX, UNET
), and Discrete Power Device,SiC, GaN/AlGaN technologies (
ST-I
). State-of-the-art based statistical models, based on hardware and/or TCAD Statistical PV-aware models for planar bulk CMOS generation devices (down to 32nm) (
POLI, UNGL, UNET, NXP, AMS
) Due date M18
DONE
M30 PV-aware circuit-level models for 45nm analog CMOS technology (
ST-F2
) Modeling of additional variability sources of 3-dimensional device architectures, for new device architectures for 22nm (
LETI, UNGL, UNET
) M33 Task Leader:
Project Review Meeting Catania, Nov. 9-10, 2010
Local Statistical Line edge roughness Variations in statistical models: sources Global Process Die to die Local Systematic ( Layout dependent ) H.Tsuno, Sony, VLSI 2007 Poly Si granularity Wafer to wafer Source: A.Asenov
Channel dopants
42
Across chip
UNGL Deliverable 2.5.1
• Extraction of accurate uniform compact models, DC and AC NMOS I D V D Capacitance fit at V D =0V NMOS with substrate bias Capacitance fit at V D =1.1V
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UNGL Deliverable 2.5.1
• Selection of optimal statistical parameter set and statistical compact model extraction • Preservation of parameter correlations Distribution of fitted error for different parameter sets NMOS and PMOS parameter correlations 44 Catania, Nov. 9 & 10, 2010
Design inputs Circuit environment VDD, T, … Settings for Variations: Corners/ MC/ DOEs Netlist extracted from Layout Statistical Models for Circuit Simulation Spice model Nominal Variations: Global Local Corners construction Layout Proximity / Middle end Parasitics Statistical models: MC, Corners Core Compact model Complete simulation file Simulation engine Elementary Circuit Responses Design Analysis Distributions Corners Yield
45
T2.5 action items
• Task 2.5: compact modeling – D2.5.2 (M30):
» Statistical PV-aware models for planar bulk CMOS generation devices (down to 32nm) (POLI, UNGL, UNET, NXP, AMS )”
AI (STF2, Dec 2010): To clarify if D2.5.3 contribution (45nm Analog) effectively transforms into D2.5.2 contribution (32nm Digital) – D2.5.3 (M33):
« PV-aware circuit-level models for 45nm analog CMOS technology (ST-F2). Modeling of additional variability sources of 3 dimensional device architectures, for new device architectures for 22nm (LETI, UNGL, UNET )”
=> AI(WP leader, same as AI as D2.2.5, Nov 2010): to contact LETI, cc UNGL on demonstrator devices (FDSOI, Finfets ?,…) and associated templates. Backup template devices already available at UNGL. Need decision latest Feb 2011.
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Contents
• WP2 introduction • Task 2.1 to 2.5 summary • Matrix, Gantt chart, relation with other Wps • Action points from meeting
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Technologi es
Task
HVMOS Planar CMOS NVM FDSOI
65nm 45nm 32nm 41nm WP2 meeting Domain overview per task and partner
Process simulation
2.1
Device simulation
2.2
Electrical Charact.
2.3
Reliability
2.4
Compact Modeling
2.5
AMS TUW UNGL POLI SNPS (STF2) UNGL POLI (STF2) UNET NMX SNPS IMEP (STF2) IMEP STF2 IMEP STF2 UNET NMX LETI IMEP AMS TUW UNCA UNGL UNET (NMX) AMS TUW UNGL POLI STF2 NXP UNGL UNET NMX LETI
Finfets, MUG, GAA SiC Power MOS AlGaN-GaN HEMT
STI STI STF2 NXP STI STI IMEP STI STI PV aware tools and methods are of common interest; they are developped and applied to a wide spectrum of technologies (Project book rev2 v2.4.1).
Significant communalities of technology targets, except different ones for Process and Device simulation. (not funded) Catania, Nov. 9 & 10, 2010
WP2/ Task 2.4 contributions
Effects -> Technologies
HV mos 65nm cmos 45nm cmos
HCI
AMS TUW UNCA (NXP) UNGL UNCA (NXP) NVM Thin Si
NBTI
AMS TUW UNGL
TDDB RTN/Trapping/ De-trapping SBD/BD
UNGL UNET (NMX) IMEP AI(all, end 2010): WP2 and per Task work matrix completion
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MODERN General Meetings Catania, Nov. 9 & 10, 2010
WP2 meeting: Gantt chart
WP2
T2.1
D2.1.1
D2.1.2
T2.2
D2.2.1
D2.2.2
D2.2.3
D2.2.4
D2.2.5
D2.2.6
T2.3
D2.3.1
D2.3.2
D2.3.3
D2.3.4
T2.4
D2.4.1
D2.4.2
D2.4.3
T2.5
D2.5.1
D2.5.2
D2.5.3
T2.1: PV-aware process simulation D2.1.1
D2.1.2
T2.2: PV-aware device simulation D2.2.1
D2.2.2
D2.2.3
D2.2.4
D2.2.5
D2.2.6
D2.3.1
D2.3.2
D2.3.3
D2.3.4
D2.4.1
D2.4.2
D2.4.3
T2.5: PV-aware compact modelling D2.5.1
D2.5.2
D2.5.3
01/03/2009 01/03/2009 01/03/2010 01/03/2009 01/03/2009 01/03/2009 01/03/2009 01/03/2010 01/03/2010 01/03/2010 01/03/2009 01/03/2010 01/09/2010 01/09/2010
30/11/2011
28/02/2011 31/05/2010 31/05/2011 29/02/2012 31/08/2009 28/02/2010 31/08/2010 28/02/2011 31/05/2011 29/02/2012 28/02/2010 31/08/2010 31/08/2011 29/02/2012 D2.1.1
D2.2.1
D2.2.1 D2.2.2 D2.3.1
D2.2.1 D2.2.2
D2.2.1 D2.2.4
D2.2.1 D2.2.3
D2.2.2
D2.2.4 D2.2.5
D2.2.3 D2.3.1
01/03/2009 01/03/2009 01/03/2009 01/03/2009 01/03/2009 01/03/2009 01/03/2009 31/08/2009 30/11/2011 D2.2.1
28/02/2011 D2.4.1
30/11/2011 D2.4.1 D2.4.2 D2.2.2 D2.2.3
30/11/2011 31/08/2010 31/08/2011 D2.2.2 D2.2.3 D2.3.1 D2.2.4 D2.3.3
D2.2.2 D2.2.3 D2.5.1
AI(all): requires completion (links with other WPs), and review by email within 2 months
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WP2 action items
• WP2 – Need to Complete WP2 matrix + 1 matrix per task – Need to Complete Gantt chart AI (all, Jan 2010). WP leader to send email for feedback collection Nov 2010. WP2 members to feedback to Task Leaders, who will compile and update per task.
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Contents
• WP2 introduction • Task 2.1 to 2.5 summary • Matrix, Gantt chart, relation with other Wps • Backup: List of Action points from meeting
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WP2 action items
• WP2 – Need to Complete WP2 matrix + 1 matrix per task – Need to Complete Gantt chart => AI (all, Jan 2010). WP leader to send email for feedback collection Nov 2010. WP2 members to feedback to Task Leaders, who will compile and update per task.
• Task 2.1: Process simulation –
D2.1.2 (M27): « Enhanced process simulation including treatment of PV for Discrete Power Device, HV-CMOS, SiC, GaN/AlGaN technologies, interfaced to commercial TCAD tools (ST-I, AMS, TUW) »
AI (STI, AMS, M27): HVMOS and AsGaN-SiC device sensitivity analysis to Process variations to be validated on HW data available from D2.3.2
• Task 2.2: Device simulation –
D2.2.4 (M24): « Forecast of the magnitude of statistical variability in 32nm planar bulk CMOS devices via device simulation (UNGL, IMEP, UNET
)” AI (STF2, Nov 2010): to provide TCAD decks. 5-way NDA between UNGL-UNET-SNPS POLI-ST applies.
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WP2 action items
• Task 2.2
– D2.2.5 (M27):
« TCAD based assessment of PV effects of potential 22nm device architectures (UNGL )”
=> AI (WP leader, Nov 2010): contact LETI on demonstrator devices (FDSOI, Finfets?,…) and associated templates. Backup template devices already available at UNGL. Need decision latest Feb 2011.
– D2.2.6 (M36):
« Sensitivity analysis of Non Volatile Memory device performance as a function of individual trap position (NMX,UNET) . Toolbox (methodologies, models, tools) to make dominant variability effects accessible to industrial usage of TCAD. Outlook to 16nm device architecture robustness using MASTAR (UNGL, STF2 )”
=> AI(T2.2 Leader): Contact SNPS if they intend to contribute to toolbox
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WP2 action items
• Task 2.3: Characterization and simulation verification – D2.3.2 (M18)/D2.3.4 (M36):
« 1/f noise dispersion”
=> AI (WP leader): Ask NXP about plan to develop compact model within Modern – D2.3.4: (M36)
« Report on high-level models, both analytical and graphical , for PV of in Non-Volatile-Memory devices (NMX )”
AI change title: « Report on high-level models, both analytical and graphical , for PV of devices in Non-Volatile-Memory technologies (
NMX
)” • Task 2.4: Reliability – D2.4.2 (M24): «
Hardware results of aging measurements available, on planar bulk CMOS technologies (AMS, TUW, UNET, UNCA )”
=> AI (UNCA, working with NXP): addition of sub-Vt slope to Vt figure for HCI effects – D2.4.3 (M33) «
Implementation of statistical degradation effects into aging models, hardware calibration of degradation effects (IMEP, AMS, TUW, UNGL, UNET, UNCA )”
AI (AMS, TUW): Implementation of process variations in NBTI/HCI degradation compact models for HV devices (Challenging, nevertheless achievable with some approximations to physics) AI (UNGL): UNGL to clarify contribution to NBTI/HCI compact models
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WP2 action items
• Task 2.5: compact modeling – D2.5.2 (M30):
» Statistical PV-aware models for planar bulk CMOS generation devices (down to 32nm) (POLI, UNGL, UNET, NXP, AMS )”
AI (STF2): Clarifies if D2.5.3 contribution (45nm Analog) transforms into D2.5.2 contribution (32nm Digital) – D2.5.3 (M33):
« PV-aware circuit-level models for 45nm analog CMOS technology (ST-F2). Modeling of additional variability sources of 3-dimensional device architectures, for new device architectures for 22nm (LETI, UNGL, UNET )”
=> AI(WP leader, same as AI as D2.2.5, Nov 2010): contact LETI on demonstrator devices (FDSOI, Finfets ?,…) and associated templates. Backup template devices already available at UNGL. Need decision latest Feb 2011.
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