Transcript Document

MODERN ENIAC WP2 Meeting
Crolles, 2009 June 22
Feedback to Board meeting
Crolles, 2009 June 23
Project Review Meeting
Crolles, June 22, 2009
07/07/2015
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Contents
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WP2 meeting overview
T2.1
T2.2
T2.3
T2.4
T2.5
Project Review Meeting
Crolles, June 22, 2009
07/07/2015
2
Relation among Work Packages
Project Review Meeting
Crolles, June 22, 2009
07/07/2015
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WP2 Key Figures
• 5 Tasks/18 deliverables (reports):
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Process (2) & device (6) simulation
Electrical characterization (4) & Reliability(3)
Compact modeling (3)
Covering both Tools/Methodology improvements and Application results
• Wide spectrum of technologies & devices applications
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45nm: planar Mosfet
32nm: planar Mosfet, FinFet
22nm: FD SOI Mosfet
State-of-art NVM
Discrete Power Device, SiC, GaN/AlGaN
HV CMOS
• TOTAL EFFORT: 638.6 PM =53.22 PY
• Reference: MODERN Rev2.1.7 project description
Project Review Meeting
Crolles, June 22, 2009
07/07/2015
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WP2 Task Definition and Contributors
WP2
Process/Device to Compact Modeling
Contributors
T2.1
PV aware process simulation
ST-I, AMS, TUW
T2.2
PV aware device simulation
UNGL, IMEP, UNET, NMX, POLI, STF2,
ST-I, SNPS
T2.3
Electrical characterization of PV, software
(TCAD) / hardware comparison & calibration
NXP, AMS, IMEP, UNET, LETI, NMX,
STF2, ST-I
T2.4
Correlation between PV and reliability,
reliability modeling
AMS, IMEP, UNET, TUW, UNCA,
UNGL
T2.5
PV aware compact modeling
UNET, AMS, LETI, NMX, NXP, POLI,
STF2, ST-I, UNG
Project Review Meeting
Crolles, June 22, 2009
07/07/2015
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WP2 Task Leaders
WP2
STF2
[email protected]
T2.1
ST-I
[email protected]
T2.2
UNGL
[email protected]
T2.3
NXP
[email protected]
T2.4
AMS
[email protected]
T2.5
UNET
[email protected]
Project Review Meeting
Crolles, June 22, 2009
07/07/2015
6
WP2 June 22 meeting at a glance
• PV aware Process Simulation T2.1:
– Only ST-I and AMS/TUW contributing.
– Therefore need to re-define D2.1.1 and D2.2.2
– Application focus: Discrete – HV CMOS
• PV aware Device Simulation T2.2:
– Device templates (generic TCAD files for PV aware device
simulation):
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Cmos 45/32nm: ST (under NDA in progress
NVM: NMX
Finfets: NXP support decision would help
FD SOI: Leti?
GaN: ST-I?
– Need to link Silicon T2.3 results and Device Simulation
=> access to HW needs to be addressed in tasks 2.3/2.4
– GSS company as UNGL sub-contractor
Project Review Meeting
Crolles, June 22, 2009
07/07/2015
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WP2 June 22 meeting in a glance
• PV aware Characterization T2.3
– Need meeting for Silicon data review nov 2009
– UNET needs access to 45nm silicon HW
– Request to be sent to NXP and ST
• PV aware Characterization T2.4
– UNCA needs access to 45nm silicon HW
– Request to be sent to NXP and ST
• PV aware Compact Modeling T2.5
– Need to better identify WPx requirements on model cards availability
• Status of WP2 deliverables: on track
• Funding: Italy and UK contracts not signed yet
Project Review Meeting
Crolles, June 22, 2009
07/07/2015
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T2.1 Task 1/1
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Task T2.1: PV-aware process simulation
Process simulation tools will be extended to include the impact of variations
in TCAD simulations especially in etching and deposition processes; an
interface to commercial process and device simulation programs will be
developed. Process simulations for the extraction of behavioral models will
be performed. In addition it is intended to build up an interface between the
process simulation environment and the semiconductor FAB to obtain
equipment parameters which affect variability.
Partners: ST-I, AMS, TUW
In the analysis and modelling of PV ST-I wants to link process information
out of the silicon manufacturing facility into TCAD environment in order to
take into account inevitable process variations and doping fluctuations with
the objectives to create a behavioural model of the process to be simulated
and to perform statistical process analysis and process optimization to
improve parametric yield. AMS and TUW will focus on TCAD process
simulation to reflect major sources for PV in 0.35um, 0.18um and 0.13um
CMOS and HV technologies; main inline/equipment parameters will be
taken into account. TCAD based statements about pros and cons of
emerging device options will be given concerning variability. The
methodology will be compared to the one used in task 2.2.
Project Review Meeting
Crolles, June 22, 2009
07/07/2015
9
Process simulation: T2.1 Deliverables
Need to re-define deliverables, with emphasis on ST-I and AMS technologies
(Discrete, Analog/HV CMOS).
Ref
Deliverable/ Contributors
Due date
D2.1.1
First version of process simulator including treatment of PV for mainstream
CMOS technologies, and Discrete Power Device,SiC,GaN/AlGaN
technologies, interfaced to commercial TCAD tools
(ST-I, AMS, TUW)
M15
D2.1.2
Enhanced process simulator for treatment of PV for mainstream CMOS
technologies, and Discrete Power Device,SiC,GaN/AlGaN technologies,
interfaced to commercial TCAD tools
(ST-I, AMS, TUW)
M27
Task Leader: [email protected]
Project Review Meeting
Crolles, June 22, 2009
07/07/2015
10
T2.1 Review Summary. ST-I, AMS, TUW
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Activity done so far
– Specification for Manufacturing-TCAD interface launched
• Scope is common spec for HV CMOS and Discrete technologies
– Discrete:
• Statistical data collection: starting activity
– HV CMOS PV:
• Statistical data collection and analysis done (0.35um)
• TCAD set-up, calibration, and critical PV selection on going
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Plan for D2.1.1 deliverable: on track
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Issues
– Major: Need to redefine D2.1.1 in project book. Purpose of R&D need is met in
Discrete and HV CMOS technologies.
– Minor: TUW device simulation activity would better fit with T2.1
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Interaction need: within WP2
Project Review Meeting
Crolles, June 22, 2009
07/07/2015
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T2.2 Task (1/2)
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Task T2.2: PV-aware device simulation
Focus in this task is on activities to include variability in device simulation tools. TCAD will be used to assess
various device architectures in standard CMOS but also in other technologies concerning variability, to identify
major sources for variability on simulation level already; process sensitivities will be investigated. New methods will
be developed to generate statistical circuit simulation parameter through TCAD, with smart approaches (other than
brute force). Furthermore mixed mode device/circuit simulations will be carried out.
Partners: UNGL, IMEP, UNET, NMX, POLI, STF2, ST-I, SNPS
UNGL will identify the sources of statistical variability in 45 nm CMOS and predict the statistical variability in 32
and 22 nm technology generation devices and advanced NVM devices based on statistical 3D drift diffusion
simulations. The simulations will be carried out with the UNGL 3D ‘atomistic’ statistical simulator GARAND. This
semi-commercial tool includes random discrete dopants, line edge roughness, poly silicon and high-k granularity,
and interface and body thickness variations. Methodology will be developed to capture the transport variability
associated with the above variability sources using 3D Monte Carlo simulations and the results will be folded in the
Drift-Diffusion simulations using appropriate mobility models. The simulator will be interfaced to the TCAD process
simulation tools developed in task 2.1 and validated in respect of 45 nm technology devices from partners in the
consortium. This will allow the identification of the major sources of statistical variability at this technology
generation. The simulator will be than used to predict the magnitude of statistical variability in 32 nm Ultra Thin
Body SOI transistors developed by LETI and 22 nm technology devices with novel architecture. ST-I will translate
behavioral models which take into account the statistical information of process fabrication steps into device
electrical performance. Parameter sensitivities will be studied for a wide range of electrical performance. The
objective of the POLI contribution is to investigate efficient methods to develop physics-based statistical models
and PV aware modeling with the use of smart TCAD approaches, based on sensitivity evaluation techniques, and
to link such approaches to suitable compact model structures. The main object will be mainstream planar bulk
down to CMOS 45/32nm. Starting from DC sensitivities and statistical analysis, linking random process
parameters to random "static" device performances (such as the threshold voltage), extensions to the dynamic
case, based on time- and/or spectral-domain approaches, will be considered. STF2 will extrapolate the results
generated during the first 24 months of MODERN to more advanced nodes. Various advanced device
architectures such as planar Ultra-Thin-Body and BOX (UTB²), FinFET, or Planar Double Gate All-Around will be
compared in terms of robustness to variability (both process-induced and local). For this comparison 16nm design
rules will be estimated and used furtheron to estimate the minimum SRAM bit-cell size for each structure
guaranteeing a proper functionality of a 64Mbit array.
Project Review Meeting
Crolles, June 22, 2009
07/07/2015
12
T2.2 Task (2/2)
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Task T2.2: PV-aware device simulation (cont’)
The device simulation will be carried out using the analytical software MASTAR, which has been
used to calculate ITRS roadmaps 2005 and 2007. IMEP will focus on the modeling of variability in
advanced CMOS devices (bulk and thin film SOI), and on atomistic simulations of variability in thin
film CMOS devices. The work will be carried out in cooperation with STF2. Specific modelling of
the influence of new variability sources like metal gate work function fluctuations, thin film
thickness variation, RTS noise will be investigated using TCAD and simple analytical models. The
latter will also be introduced into MASTAR platform, in collaboration with STF2, for new
technology specification prediction. UNET will put emphasis on the device simulation of memory
cells, transistors for high-performance logic circuits and for low-power mixed-mode applications:
At the beginning a methodology will be defined to evaluate the impact of process tolerances and
intrinsic variability on the dispersion of electrical parameters with computationally efficient TCAD.
Viable modelling approaches to efficiently incorporate new physics phenomena and their
fluctuations in future devices will be worked out, taking into account the impact of variations of the
dielectric thickness, channel doping and stress conditions. In addition a methodology will be
defined to evaluate the impact of PV on a single cell within a memory array. Mixed-mode
device/circuit simulation methodologies will be looked into to analyze the impact of fluctuations on
the performance of simple digital and analog circuit blocks. The objective of the work of NMX is to
study the impact random dopant, edge roughness, and trap position on scaled NVM cells of Non
Volatile Memory technologies from 32nm technology node and below. It’s about to push the
implementation of the capability to treat individual dopant atoms and individual traps instead of
dopant concentrations used nowadays in commercial device simulators. SNPS will enhance the
methods of modeling process induced geometrical variations of the devices. The goal is to find
methods that allow the direct calculation of uncorrelated geometrical variations on device
electrical characteristics. SNPS will evaluate and improve its existing TCAD models with respect
to the treatment of individual dopants and traps in silicon in device modelling tools.
Project Review Meeting
Crolles, June 22, 2009
07/07/2015
13
Device Simulation: T2.2 Deliverables
Ref
Deliverable/ Contributors
Due date
D2.2.1
Assessment of state-of-the-art TCAD methodology and usability concerning PV for
industrial purposes including identification of current deficiencies of tools (UNGL)
M6
D2.2.2
Device simulation analysis of dominant variability sources in 45nm planar bulk CMOS
technologies, and Discrete Power Device,SiC, GaN/AlGaN technologies.
Prototype implementation of the treatment of individual dopants and traps in the device
modeling tools
(UNGL, UNET, NXP, ST-I, SNPS)
M12
D2.2.3
Device simulation analysis of dominant variability sources in state of-the-art NonVolatile-Memory technologies (UNET, UNGL, NMX, SNPS)
M18
D2.2.4
Forecast of the magnitude of statistical variability in 32nm planar bulk CMOS devices via
device simulation (UNGL, IMEP, UNET).
Efficient compact model extraction procedures for modeling process variations and
device fluctuations (NXP, UNET, POLI)
M24
D2.2.5
Application of mixed-mode device-circuit simulations for the analysis of the impact of
fluctuations (UNET)
TCAD based assessment of PV effects of potential 22nm device architectures (UNGL)
M27
D2.2.6
Sensitivity analysis of Non Volatile Memory device performance as a function of
individual trap position (NMX)
Toolbox (methodologies, models, tools) to make dominant variability effects accessible
to industrial usage of TCAD, outlook to 16nm device architecture robustness using
MASTAR (UNGL, STF2)
M36
Task Leader: [email protected]
Project Review Meeting
Crolles, June 22, 2009
07/07/2015
14
T2.2 Review
Deliverables
D 2 .2 .1 D 2 .2 .2 D 2 .2 .3 D 2 .2 .4
0 8 /0 9 0 2 /1 0 0 8 /1 0 0 2 /1 1
U N GL T he U nivers ity of G las gow
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P
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I M E P I M E P - L A H C L aboratory
P
U N E T C ons orzio N azionale I nt. N ano
P
L
P
NMX
N umonyx I taly Srl
P
P O L I P olitec nic o di T orino
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ST F2 ST M ic roelec tronic s (C rolles 2 ) SA S
ST - I
ST M ic roelec tronic s S.r.l.
P
SN P S Synops ys Switzerland L L C
P
P
For each deliverable
• Identify contributing partners
• Identify deliverable leaders
• Taking charge of Deliverables
Project Review Meeting
Crolles, June 22, 2009
07/07/2015
15
D 2 .2 .5 D 2 .2 .6
0 5 /1 1 0 2 /1 2
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T2.2 Review: Activity done so far
• Discussion and partial agreement on template
devices
Bulk MOSFETs
45nm STF2 - availability: possibly recalibration
32nm STF2 - availability? 5way NDA in progress
22nm ???
16nm ???
FD SOI MOSFETs
32nm LETI (T2.3) Is it confirmed by Leti?
22nm LETI (T2.3)
16nm LETI (T2.3)
Project Review Meeting
Crolles, June 22, 2009
07/07/2015
16
T2.2 Review: Activity done so far
• Discussion and partial agreement on template
devices
FinFETS
22nm ??? Note that NXP might provide HW within T2.3
16nm ???
None Volatile Memory (NVM)
NMX, under NDA
SiC
ST-I, conditions to be defined
GaN/AlGaN
ST-I, conditions to be defined
Project Review Meeting
Crolles, June 22, 2009
07/07/2015
17
T2.2 Review: Activity done so far
• Review of needs for statistical TCAD simulation
– All major semiconductor players contacted
– 25 responses so far from TCAD and device engineers
including NEC, Fujitsu, Chartered, IBM, Freescale,
NXP, Panasonic, Intel, Numonix, Toshiba, Infineon,
Samsung, Renesas, Hitachi, Altera, Sony
– TSMC declined to participate
– Still awaiting response from ST-F
Project Review Meeting
Crolles, June 22, 2009
07/07/2015
18
T2.2 Review: Plan for D2.2.1
• Collect and analyze the survey of requirements
• Invite TCAD tool vendor to declare the
capabilities of their tools to assess the
requirements
• Prioritization related to the MODERN partners
needs
Project Review Meeting
Crolles, June 22, 2009
07/07/2015
19
T2.2 Review: Plan for D2.2.2
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Finalize the relevant template devices
Identify the players
Complete the necessary NDAs
Identify the variability sources to be included in
the simulations
• Agree on specifications and parameters
describing the variability sources
• Agree on simulation sets and perform simulations
• Collect and compare results
Project Review Meeting
Crolles, June 22, 2009
07/07/2015
20
T2.2 Review: Plan for D2.2.2
• In order to receive half of its MODERN funding from
Scottish Enterprise UGLA had to create a company Gold
Standard Simulations (GSS)
• The company will provide simulations services of
statistical variability using software developed by UGLA
and Grid technology
• UGLA will subcontract production simulations of 45nm,
32nm and 22nm devices to GSS
• GSS will offer similar cervices to other companies on
commercial basis
• GSS will also offer services in statistical compact model
extraction, statistical circuit simulation and statistical
standard cell characterization using in-house tools
Project Review Meeting
Crolles, June 22, 2009
07/07/2015
21
T2.2 Review: Issues
• Ensure that the simulated and the measured
devices are consistent
• Italy and UK contracts not signed yet…
• Agree on tool features definition (D2.2.1=>D1.1)
– Integration in SNPS platform
– Issues on 3D meshing strategy and mobility models
• Confirm time line for tool availability
– M12 for doping/traps (D2.2.2), M24 for geometry
(D5.3.2)
• Choose best benchmarks
Project Review Meeting
Crolles, June 22, 2009
07/07/2015
22
T2.3 Task (1/3)
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Task T2.3: Electrical characterization of PV, software (TCAD) / hardware comparison & calibration
Basic effects of PV will be characterized based on hardware in different technologies, ranging from mainstream
CMOS 45/32nm to new device architectures suitable for 22nm CMOS. Other technologies like NVM or SiC,
GaAn/AlGaN power and RF devices will complement the activities. In addition for “non pure digital logic
technologies” the devices studied will span over many technology generations, so the PV-methodologies will cover
a wide spectrum of devices. In general major sources for PV will be identified and characterized wrt/ further
scaling. Variability effects and their sensitivities will be investigated from planar bulk device concepts to new
architectures on SOI in 2D or 3D. Device simulation results will be compared to measurements and will be
calibrated on hardware data to verify PV methodology and physical understanding of major sources of PV in above
technologies. It has to be emphasized that there is a strong link between some activities in WP2.3 and in WP5.1
(silicon demonstration: “test structures for PV analysis”), since test structures and their electrical characterization
can be considered as an important step towards demonstration already.
Partners: NXP, AMS, IMEP, UNET, LETI, NMX, STF2, ST-I
In this task STF2 will deal with the experimental characterization and root cause analysis of intra-field, intra-wafer
variability and transistor matching in 45nm planar CMOS devices. As variability becomes a major concern for
analog, but also for digital applications such as SRAM, it is mandatory to quantify and model this variability at
different scales: local fluctuations (matching), intra-field and intra-wafer level. It is also useful for device
optimization to identify the electrical parameters sensibility to each type of fluctuation. The determination of the
variability cause at an electrical parameter level gives some information on the process root cause of the
variability. IMEP will focus on the electrical characterization of variability in advanced CMOS devices (bulk and thin
film SOI) and develop new methodologies for the measurements of MOSFET parameter variability (metal gate
work function, thin film thickness variation, noise, etc.) based on experimental procedures and data analysis on
various CMOS technologies with bulk or thin film architectures. This work will be carried out in collaboration with
STF2. AMS will focus on the development of a methodology for generating statistical circuit simulation parameters
(SPICE Monte Carlo models). Critical features of the methodology are the selection of PCM parameters most
sensitive to process variations and the determination of the most accurate statistical mapping between simulated
PCM parameters and SPICE parameters. Test-structures for intra and inter die variability will be placed on silicon
as benchmark structures for TCAD simulations on one hand and in order to obtain the statistical data for the
needed model card including corner and MC set on the other hand.
Project Review Meeting
Crolles, June 22, 2009
07/07/2015
23
T2.3 Task (2/3)
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Task T2.3: Electrical characterization of PV, software (TCAD) / hardware comparison &
calibration (cont’)
The activities of NXP form part of a continuing effort to measure and understand the physics
behind process variations and device performance fluctuations in the most advanced CMOS
process nodes. Process variability is characterized in terms of parametric variations and
fluctuations of all devices that are relevant for a particular node. This includes DC characterization
of devices (MOSFETs of various types, (parasitic) bipolar transistors, and passive components as
resistors and capacitors) as well as low frequency (1/f) noise characterization. The objectives
range from making a systematic ranking of sources of variability (process variations, layout related
effects and random parametric fluctuations) in relatively mature 65-45 nm CMOS processes, to
the assessment of benefits and/or fluctuation showstoppers in the more advanced (40 and 32 nm)
nodes that are still in the implementation phase. The first being of utmost importance for enabling
realistic circuit and system designs in the coming years, the latter for assessing the possible
benefits of moving to completely new cell libraries and multi billion device systems based on
stretched technology architectures. Major deltas concerning sources for variability will be
identified. Investigations will be performed on concept level and on device level as input for
respective modeling activities in WP2.5 and circuit simulation activities in WP3 later on. Results
will be compared to those of LETI who will focus its work on PV in fully depleted SOI technologies.
The main objectives are to identify and model the specific sources of variability, and to evaluate
the benefits of such a technology, compared to standard CMOS bulk. To assess and understand
the benefits and limitations of FDSOI technologies, LETI will characterize the variability
parameters for undoped devices, considering various process optimizations (Si film thickness,
strained Si, Gate work function tuning, LDD implants...), extract variability model parameters and
compare FDSOI variability with standard Bulk CMOS (considering the same level of technological
maturity).
Project Review Meeting
Crolles, June 22, 2009
07/07/2015
24
T2.3 Task (3/3)
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Task T2.3: Electrical characterization of PV, software (TCAD) /
hardware comparison & calibration (cont’)
UNET will concentrate on experimental methodologies for characterization
of PV on test structures, single cells or simple arrays and on methodologies
for evaluation of cell statistics on array performance, for 45 and 32nm
planar CMOS and for Non Volatile Memory technologies. NMX will put his
focus on the development of: methodologies for measurement, modeling
and verification of mismatch (local variations) including study of bias,
temperature, spacing and layout effects, and on methodologies for
measurement, modeling and verification of global variations in electrical
parameters (both spreads and correlation) for active, passive devices and
interconnects. This will be done on logic devices of NVM technologies with
gate oxide thickness ranging from 30 to 400A belonging to 65, 45 and 32
nm technology nodes. Some benefits of cooperation amongst the partners
can be sharing of characterization methodologies in production, comparing
of PV root cause analysis results, or benchmarking of statistical modeling
approaches. Test devices in different technologies as SiC PowerMOS and
diode, and AlGaN/GaN HEMT will be fabricated by ST-I. A full electrical
characterization will be performed to study the effects of PV on the
performance of such devices, e.g. on the frequency behavior of HEMTs and
high power test devices.
Project Review Meeting
Crolles, June 22, 2009
07/07/2015
25
Electrical Characterization: T2.3 Deliverables
Ref
Deliverable/ Contributors
Due date
D2.3.1
Characterization of the influence of variability sources in planar bulk CMOS devices
down to 45nm (STF2, IMEP, UNET, NXP)
Experimental characterization of Non-Volatile- Memory devices in the presence of PV
(NMX, UNET)
Parametric mismatch fluctuation effects in 32 nm FinFETs, first PV results on 22nm
FDSOI MOSFETS (LETI, NXP)
M12
D2.3.2
Characterization of major sources of PV in SiC technologies/devices, and AlGaN/GaN
HEMT devices (ST-I)
Report on 1/f noise dispersion behavior in 45nm bulk CMOS (NXP)
M18
D2.3.3
Identification of most relevant process variations in planar bulk CMOS devices down to
32nm, parameter fluctuation effects based on hardware (STF2, NXP, UNET, AMS)
Sources for PV in new device architectures, suitable for 22nm CMOS; major deltas in
comparison to standard planar bulk CMOS (IMEP, NXP, LETI)
M30
D2.3.4
Report on high-level models, both analytical and graphical , for PV of Non-VolatileMemory devices (NMX)
Report on 1/f noise dispersion behavior in 32 nm planar bulk CMOS (NXP)
M36
Task Leader: [email protected]
Project Review Meeting
Crolles, June 22, 2009
07/07/2015
26
WP2 T2.3 Review
Overview / Conclusions
•
No reactions received from
– UNET on 45 nm bulk status
– LETI on FD-SOI
– ST-I on SiC and AlGaN/GaN devices
•
Plan for deliverables D2.3.1 & D2.3.2 : no roadblocks reported / foreseen
•
should we plan a contact meeting to share & compare results (D2.3.1)
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Issues
– NMX: Near term under discussion cooperation with STF (link WP2.3 – WP 5.1)
– NXP: FinFET research officially stopped
•
Interaction need with other WP, if any:
- UGLA (T2.2) stresses that measured device geometries should be aligned with
simulated ones
- NXP sees benefit of suggests sharing of simulator tuning approach
Project Review Meeting
Crolles, June 22, 2009
07/07/2015
27
T2.4 Task (1/2)
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Task T2.4: Correlation between PV and reliability, reliability modeling
The impact of process variability on existing device reliability degradation models will be clarified.
Aging measure-ments will be performed on test structures: Device degradation mechanisms will
be identified based on silicon, their effect on PV parameters will be characterized and modeled to
allow for a better description of aging during operation.
Partners: AMS, IMEP, UNET, TUW, UNCA, UNGL
UNGL will develop methodologies for the simulation of the statistical impact of NBTI and hot
carrier degradation on the MOSFET characteristics in concert with the statistical variability
sources described in T2.2 and its capture in statistical compact models. UNCA will perform aging
measurements on nano-MOSFET devices focusing on the three main reliability mechanisms: hotcarrier injection, bias-temperature instability and time-dependent dielectric breakdown. The impact
of process variation (e.g. line edge roughness, random dopant distribution, non-homogenity of the
gate dielectric) on the device reliability will be investigated and potential solutions will be
proposed. Aging models will be developed to predict device lifetime dependence on the statistical
fluctuations of geometrical and technological parameters of nano-MOSFET. Model parameters will
be calibrated with the hardware results of aging measurements. UNET will work on methodologies
to design reliability experiments that allow characterizing the impact of PV on test structures,
single cells or simple arrays, on 45nm & 32nm planar CMOS, and on Non-Volatile Memories. It
will include the development of compact models including aging effects. AMS will execute lifetime
measurements necessary for model development and the usage in SPICE simulators in 0.13um,
0.18um and 0.35um CMOS and HV technologies. The objective is to develop silicon based
models for PV and reliability correlation. Lifetime measurements will be performed on appropriate
test structures. Based on that data set, PV-aware parameter degradation models for NBTI and
HCI effects will be developed at TUW. Since in particular degradation caused by NBTI is known to
recover quickly once the stress is removed, emphasis will be put on a proper description of the
dynamical properties of the degradation.
Project Review Meeting
Crolles, June 22, 2009
07/07/2015
28
T2.4 Task (2/2)
• Task T2.4: Correlation between PV and reliability, reliability
modeling (cont’)
• With future technology nodes it is becoming more and more critical
to consider statistical and deterministic variations for ensuring the
design goal at time of manufacturing as well as for the proposed
lifetime. IMEP will investigate based on mixed mode TCAD
simulation and on analytical models the SBD/BD failure occurrence
impact at device level on device characteristics and at elementary
circuit level on subsequent circuit functioning. These studies will be
extended to new device architecture featuring thin silicon film
(MugFET, GAA), which will be benchmarked in term of reliability
robustness to bulk devices. This will require a detailed analysis of
the SBD/BD occurrence and characterization on actual FD-SOI or
GAA devices. The work will be carried out in collaboration with
STF2.
Project Review Meeting
Crolles, June 22, 2009
07/07/2015
29
Reliability: T2.4 Deliverables
Ref
Deliverable/ Contributors
Due date
D2.4.1
Specification of considered degradation effects, modeling
approaches and device parameters (UNGL, TUW)
M6
D2.4.2
Hardware results of aging measurements available, on planar bulk M24
CMOS technologies (AMS, TUW, UNET, UNCA)
D2.4.3
Implementation of statistical degradation effects into aging models, M33
hardware calibration of degradation effects (IMEP, AMS, TUW,
UNGL, UNET, UNCA)
Task Leader: [email protected]
Project Review Meeting
Crolles, June 22, 2009
07/07/2015
30
T2.4 Review (2/1)
(AMS, IMEP, UNET, TUW, UNCA, UNGL)
•
Activity done so far
–
–
–
–
–
–
–
–
–
•
Collect experimental data in order to develop a physically based degradation model for
HCI and NBTI
LV MOS first, HV MOS final goal (AMS, back-up slides)
Measurement done on ‘golden wafers’ ( PV is neglected, AMS)
The initial NBTI results from the model are validated against the numerical results
(TUW, back-up slides).
Well established methodology for simulation of statistical aspects of NBTI (UGLA,
back-up slides)
Survey of requirements for statistical reliability simulation (UGLA)
UNCA: Needs samples from industrial partners. Collaboration with ST-I
IMEP: Collaboration with STF2
UNET: Collaboration with STF2
Plan for D2.4.1 deliverable
–
–
–
–
–
Discuss with T2.5 the most interesting devices for the demonstrator, with T2.1 the
process parameters to take into account.
Initial physics-based analytical model for NBTI to implement in circuit simulator
Survey of degradation effects TUW, UGLA
Time dependent modeling of degradation TUW
Statistical modeling of degradation UGLA
Project Review Meeting
Crolles, June 22, 2009
07/07/2015
31
T2.4 Review (2/2)
(AMS, IMEP, UNET, TUW, UNCA, UNGL)
•
Issues
–
–
•
Near term (for D2.4.1 deliverable): none
Mean term:
• How to measure PV influence on reliability?
• How to include PV in a reliability model?
• Experimental results which captures the dynamics like recovery, bias
dependence of recovery, etc. to validate the models
• Find a correlation between parameters related to reliability and process
variability.
Interaction need with other WP, if any
–
–
Statistical simulation of variability and reliability are connected
Simulated and measured devices are identical!
Project Review Meeting
Crolles, June 22, 2009
07/07/2015
32
Well established methodology for simulation of statistical
aspects of NBTI (UNGL)
Project Review Meeting
Crolles, June 22, 2009
07/07/2015
33
Well established methodology for simulation of statistical
aspects of NBTI (UNGL)
Project Review Meeting
Crolles, June 22, 2009
07/07/2015
34
Validation of the Model (TUW)
Project Review Meeting
Crolles, June 22, 2009
07/07/2015
35
T2.5 Task (2/1)
•
•
•
•
Task T2.5: PV-aware compact modelling
PV and reliability effects have to be implemented in device compact models to be able to
accurately describe the impact of variability on circuit operation. Implementation methodologies
will be worked out and adopted in standard compact modeling.
Partners: UNET, AMS, LETI, NMX, NXP, POLI, STF2, ST-I, UNGL
UNGL will develop compact model parameter extraction strategies that capture accurately the
statistical device variability and the statistical aspects of reliability in industrial standard compact
models including BSIM, BSIMSOI and PSP. POLI will be developing PV aware compact models in
conjunction with the activities carried out in task 2.2, on the basis of the so-called sensitivity
approach. The approach will be exploited for the development of quasi-static models (through the
implementation of the DC sensitivity concept) and of dynamic models (through the implementation
of the large-signal sensitivity concept). The strategy allows very efficient compact models, also
accounting for the PV statistics, to be developed, also taking into account the correlation between
different input parameters, provided that the input statistics is modelled in closed form. Such
models will be deriving their parameters from physics-based simulations or characterizations. The
modelling strategy will be mainly applied to the CMOS 45/32nm process, but can be taken into
consideration for other technologies like GaAn/AlGaN power or RF devices as well. The compact
models will be implemented within the framework of a suitable circuit simulation platform.The aim
of the activity of ST-I is to develop a statistical Spice model for the design of complex nano-scale
IC starting from TCAD simulations directly linked to process fluctuations due to equipments
specifications. In this flow numerical techniques will be introduced in order to reduce the number
of technology CAD simulations to be performed to extract the statistical model of a single device
fabrication process and as consequence to reduce the computational costs and the time
consumed; at the same time techniques will be used to reduce the number of circuit simulations
for extraction of the statistical spice model of the IC, taking advantage of multi-objective
optimization algorithm for yield analysis in addition AMS will implement reliability effects in device
state of the art compact models in order to describe PV for circuit simulation in 0.35um, 0.18um
and 0.13um CMOS and HV technologies.
Project Review Meeting
Crolles, June 22, 2009
07/07/2015
36
T2.5 Task (2/2)
•
•
Task T2.5: PV-aware compact modelling (cont’)
STF2 will focus on the compact modelling of PV effects in bulk CMOS technology and application
to the simulation of 45nm devices for circuit design. The work goes through classification of
variability relevant sources, development of a formal description of process/device variables and
associated compact models extensions in order to allow Monte-Carlo circuit simulation. The
compact model extensions derived are intended to reflect systematic and random effects
observed in a 45nm core CMOS technology at local scale (mismatch), intra-die scale, and
interdie, and their layout dependence. NXP’s contribution will address a realistic physics based
implementation method to mimic process variations as well as device fluctuations in analog circuit
simulation using the PSP compact model. This will initially be done for all device types in a
relatively mature 45nm CMOS node using the standard bulk CMOS PSP model. Subsequently,
the methodology will be ported, adjusted and refined to more advanced 40-32 and possibly 22nm
bulk CMOS nodes. With further scaling it becomes mandatory to come up with viable analytical
modeling approaches to efficiently incorporate new physics phenomena and their fluctuations in
compact models, including quasi ballistic transport (QTB) features and the impact of variations of
the dielectric thickness, channel doping and stress conditions, and with viable compact modeling
approaches to reach the best trade-off between accuracy and statistics, including variability.
UNET will address these aspects involving new physics for 45/32nm CMOS and for non-volatile
memory technologies. NMX will in this task study a viable and effective implementation of an
analytical compact model which takes into account PV in NVM logic devices (implementation of
the characterization performed in WP2.3) and the impact random dopant, edge roughness, and
trap position on scaled NVM cells; joint activities together with UNET are planned. Collaborations
with ST-I and NMX are envisioned. Starting from BSIMSOI and an in-house PSP modified thin film
device model, LETI will develop statistical modeling of the correlations between model parameters
and variability sources for the FDSOI 22nm technologies. This will be used to classify and quantify
FDSOI variability sources.
Project Review Meeting
Crolles, June 22, 2009
07/07/2015
37
Compact Modeling: T2.5 Deliverables
Ref
Deliverable/ Contributors
Due date
D2.5.1
PV-aware circuit-level models for standard CMOS technologies (down to
45nm) (UNGL, UNET, NXP, POLI, ST-I, STF2) , and Non-Volatile-Memory
technologies (NMX, UNET), and Discrete Power Device,SiC, GaN/AlGaN
technologies (ST-I). State-of-the-art based statistical models, based on
hardware and/or TCAD
M18
D2.5.2
Statistical PV-aware models for planar bulk CMOS generation devices
(down to 32nm) (POLI, UNGL, UNET, NXP, AMS)
M30
D2.5.3
PV-aware circuit-level models for 45nm analog CMOS technology (ST-F2)
Modeling of additional variability sources of 3-dimensional device
architectures, for new device architectures for 22nm (LETI, UNGL, UNET)
M33
Task Leader: [email protected]
Project Review Meeting
Crolles, June 22, 2009
07/07/2015
38
T2.5 Review
• Activity done so far (UNGL)
– Statistical parameter extraction methodology
for BSIM and PSP
Project Review Meeting
Crolles, June 22, 2009
07/07/2015
39
T2.5 Review
Optimal parameter selection and related
accuracy
Project Review Meeting
Crolles, June 22, 2009
07/07/2015
40
T2.5 Review
Optimal parameter selection and related
accuracy
1
5
4
3
2
6
Project Review Meeting
Crolles, June 22, 2009
7
07/07/2015
41
T2.5 Review
Strategy for generating statistical parameters
As extracted
Naïve gaussian
PCA
Project Review Meeting
Crolles, June 22, 2009
07/07/2015
42
T2.5 Review
How well this reproduces figures of merit
VT
Ion
Ioff
DIBL
S
Delay
Project Review Meeting
Crolles, June 22, 2009
07/07/2015
43
WP2 Milestones (2009 March 05 fix)
Milestone
Definition
Due date
M2.1
PV aware compact models available for bulk
planar CMOS technologies down to 45nm,
TCAD/hardware
M18
D2.1.2/ D2.2.1
D2.3.1/ D2.5.1
M2.2
Identification and description of major PV
sources in non-foundry mainstream logic
technologies, cross-technology- fertilization
M21
D2.2.3
D2.3.1/ D2.3.2
D2.5.1
M2.3
Hardware results of aging measurements
available, on planar bulk CMOS technologies
M24
D2.4.2
M2.4
PV aware compact models available for
32nm bulk technology, TCAD/hardware
based
M30
D2.1.2/ D2.2.4
D2.3.3/ D2.5.2
M2.5
PV assessment for 22nm device options,
TCAD/hardware based, identification and
modeling of additional PV sources compared
to planar bulk
M33
D2.1.2/ D2.2.5
D2.3.3/ D2.5.3
Project Review Meeting
Crolles, June 22, 2009
07/07/2015
44
Thank you!
Project Review Meeting
Crolles, June 22, 2009
07/07/2015
45