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Km3net meeting Pylos, 16/4/07 S. Loucatos DAPNIA, CEA-Sacaly Front End Electronics for the KM3NET Design Study F. Guilloux*, J. Aublin, E. Delagnes, F. Druillole, H. Le Provost, S. Loucatos, J.-P. Schuller DAPNIA-CEA-Saclay, APC *[email protected] CEA DSM Dapnia Sédi Antares Front End (VFE) sum up • Antares readout electronics Ethernet Network Optical Module Analog Ring Sampler ARS Board DAQ Board • VFE requirements • 7/17/2015 First Level Functionalities: – – Discriminate signals coming from the PMT. – Measure their arrival time (0.5 ns rms precision). – – Measure their charge. – – Bufferize and Derandomize the event flow. Convert charge & time in digital data. Format the events & serialize them toward the DAQ board. Oscilloscope mode. • 2nd Level Functionalities: – Rate Monitor + rate alarm. – Filter by L1 and L2 (historical reason). – Test Led generator … • All this for a reasonable power consumption and a low cost. CEA DSM Dapnia Sédi Antares Front End (VFE) sum up • Solutions developed in the Analog Ring Sampler ASIC WaveForm : 128 memory cells Sam plingcontrol SPE Charge Integrator + Time to Voltage Converter ADC W aveform modecontrol T ime ref. clock Dyn. 2 W aveformmode 4*128memorycells (ARS0) Dyn. 1 Anode Pulse Shape Discriminator SPE mode Charge integrator SPEmodePipeline A nalogm emory cells SPE mode TVC 7/17/2015 CEA DSM Dapnia Sédi + C omp. ARS feedback • Strength and weakness + • Time precision : 500ps rms • Measure Charge of SPE without a delay added to signal path • Waveform : • Too many functionalities and parameters hard to test • Asic mainly asynchronous hard to simulate • Two ASICs per OM (to minimize dead time) Should be done by one - Fast sampling : 640MHz (up to 1GHz) - 128 memories depth for 3 amplitudes - The AMS 0.8µm is not available any more PMT output 1 GHz sampling 700 kHz A-D conversion The ARS reaches expected performances but it is too complicated : the architecture could be improved to make it simpler 7/17/2015 CEA DSM Dapnia Sédi KM3NET conservative solution: • Reuse of Antares development, updated in order to fit to KM3NET specific requirements: Antares updated requirements – OM ASIC DAQ Ethernet network – “Input” specifications (Conceptual Design 1 & 2 from WP4) • PMT electrical signal characteristics : 10’’ from Antares – Amplitude : typically a few tens of mV per PE – SPE Pulse time: all the signal is included in a window of 20ns • Reference clock frequency : few tens of MHz • Slow control protocol – Physic requirements • • • • • Measure charge with DQ/Q < 10% Measure arrival times with 0.5ns rms precision Input dynamic range~ up to 100 pe Input rate : up to 200kHz in average (SPE), max. 500kHz during 1s Discriminate multi-muon bundles Km3Net requirements – Scale effects Consumption, Design simplifications – Cost reduction Design Optimizations 7/17/2015 CEA DSM Dapnia Sédi New VFE Asic: Submarine Cherenkov rAdiated Light Electronic (SCALE) 8 bits SPE memory SPE memory SPE memory SPE memory SPE memory SPE memory SPE memory SPE memory ADC 8 Ch Dg DLL DLL DLL DLL DLL DLL DLL DLL Anode PSD L0, WF Infos L0 L0 accepted WF valid … 8 bits Switch Array Capacitors 16*32 = 512 Delay Locked Loop 7/17/2015 CEA DSM Dapnia Sédi ADC 32 Ch Dg Scale : key points • The memory Cell – Ring memories keep the past of the signal No need of external delay line – Fine Time and charge are extracted from the same unit Simplification – Fine Time is extracted from a Delay Locked Loop No ADC needed to convert time information : it is naturally digital Easy to calibrate : possible to reach ns precision from a 20MHz input reference clock with few spread (feedback loop) Clock Trigger DLL Fine Time (~6 bits) Signal IN Signal OUT Switch Capacitors Array • Multi-channels Wilkinson ADC – 8 bits resolution, ~ 5MHz conversion frequency • 7/17/2015 Architecture simplification – One Asic up to 500kHz (SPE) Queuing theory : probably 2 banks of 4 CEA DSM Dapnia Sédi memories High level language Simulations • Simulations scheme Shape discriminator Bias ADC Digital Control 8 memories 7/17/2015 CEA DSM Dapnia Sédi Digital Fifo Digital Mux High level Simulation Results – – – – – Signal filtering Dynamic range ~ 100 pe Integrated charge error < 10% Time resolution < 0.5ns rms Digital output • Charge : 10 bits • Fine Time : 6 bits • TimeStamp : 24 bits 7/17/2015 CEA DSM Dapnia Sédi Transistor level simulations are in progress Other solution under study: Multi-threshold discriminator • Discrimination strategy – Arrival time and TOT is given by several discriminators. Input Threshold1 Threshold2 SPE and others signals are treated the same way : no need of waveform The electronics is simpler : minimal analog circuitry – Is it possible to find the charge with enough accuracy knowing only the TOTs ? 7/17/2015 CEA DSM Dapnia Sédi Experimental setup ANTARES Optical Module LED triggered by generator pulses Acquisition by digital oscilloscope (2.5 GHz) 7/17/2015 CEA DSM Dapnia Sédi Number of events (over 1000 events) p.e. study Histogram of Charge Acquisition of 1000 pulses without flasher with the LED 180 Trigger on p.e. background 120 Charge integration: Q = Vi x Dti. ,or better: Simpson integral Mu = 0.363 Sigma = 0.156 160 140 100 80 60 40 20 0 0 0.2 0.4 0.6 Charge (pVs) Average track estimation 7/17/2015 CEA DSM Dapnia Sédi 0.8 1 Using the LED Runs with several LED intensities 7/17/2015 CEA DSM Dapnia Sédi Signal shape 0 Fit (scaling with LED intensity assumed) 0 -0,5 Charge = 6 SPE -1 Amplitude in V Amplitude in V -0,2 -0,4 Charge = 12 SPE -0,6 Fit -1,5 -2 -2,5 Charge = 131 SPE -0,8 -3 Charge = 35 SPE -3,5 -1 -4 0 5 10 15 20 25 30 0 5 10 15 Time in ns Time in ns Fit with sum of 4 gaussians or gamma distribution : g (t ) a t n exp(b t ) Fit on the average low amplitude signal then fit 1 parameter only (normalization). 7/17/2015 CEA DSM Dapnia Sédi 20 25 30 Relation ToT-Charge Threshold values tested: • Th= 1/3 PE • Th = 2/3 PE • Th = 1.5 PE • Th = 5 PE • Th = 10 PE • Th= 20 PE • Th = 40 PE Fit: ToT = A + B* Ln( Charge / Charge 1p.e.) Constants A et B to be determined for each threshold value 7/17/2015 CEA DSM Dapnia Sédi Charge and time reconstruction • Time is given by crossingof the first threshold. “walk” effect, need of the amplitude or charge for correction. • Charge reconstruction: 3 methods – – – 7/17/2015 Fit by a pulse form TOT ~ Ln (Q) Geometrical approximation CEA DSM Dapnia Sédi Data quality • Dispersion of time of the LED emission • Oscilloscope window reduced in amplitude Number of events (over 1000 events) Quantification noise >> electronic noise Histogram of Peak time 90 Mu = 148 Sigma = 1.19 80 70 60 50 40 30 20 10 0 140 145 150 155 time (ns) 7/17/2015 CEA DSM Dapnia Sédi 160 165 170 Fit method • Hypothesis : If all the photons are perfectly synchronous, the curve of the output of PMT is homothetic to the SPE curve. • Méthod : • We fit the average curve of SPE by a parametrised curve (A0,T0) • We fit the pairs of points of threshold crossings by this parametrised curve Charge reconstruction Error Charge reconstruction Error 20 40 30 20 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 Error (%) 10 Error (%) 0 -10 Error (%) -20 2/3pe -30 <= Threshold 1.5pe 20 10 0 0 • 0.5 Conclusions: – – – 7/17/2015 1 1.5 2 2.5 Charge/Charge SPE 3 3.5 4 4.5 5 7 Thresholds 4 Thresholds 5pe10pe 0 20 20pe 40pe<= Threshold 40 60 Charge/Charge SPE Good charge reconstruction in the entire range (~ +/- 10% RMS) Sensitive to the LED dispersion de la LED (but systematic deviation correctible) Very sensitive to the number of thresholds CEA DSM Dapnia Sédi 80 100 120 Expected time dispersion Photon arrival times in water (incl. Antares electronics DT) The dispersion of the LED emission has some similarity with Cerenkov data 7/17/2015 CEA DSM Dapnia Sédi TOT method • Hypothesis : – TOT vs Charge 50 TOT ~ Ln (Q) Time Resolution Oscillo. 40 Méthod : 30 TOT (ns) • – For each threshold we find points (A,B) such that : TOT = A + B * Ln(Q) 20 10 0 – We use then the inverse function Threshold 13mV ~ 1/3 SPE -10 0 2 4 6 8 10 12 Charge/Charge SPE Conclusions : – – – Histogram of the RMS Error 40 Sensitive to the fit for (A, B) Sensitive to double non simultaneous pulses! After strong filtering and using the correction, then approach 10% Error (%) • 30 20 10 0 -10 -20 1.5pe 5pe -30 0 7/17/2015 CEA DSM Dapnia Sédi 10 10pe 20pe 20 30 40pe 40 50 Charge/Charge SPE 60 70 80 90 100 Geometrical method • Amplitude Hypothesis : – • The simplest method to compute Seuil 3 the charge : the area under the curve Method : – Seuil 2 Linear interpolation between points Interpolation TOT1 = A+B*Ln(Q) for the last threshold – TOT1 Seuil 1 Temps 25 20 15 • Error (%) 10 5 – 0 -5 – -10 -15 -20 5pe 10pe 20pe 40pe <= Threshold -25 0 10 20 30 40 50 Charge / Charge SPE 7/17/2015 Conclusions: CEA DSM Dapnia Sédi 60 70 80 90 100 Very efficient for high charges Sensitive to the start and exponential decrease at small charge (few points) Time reconstruction + walk correction • Hypothesis : – Why go through the charge in order to correct time ? • Méthod : – For each threshold, we find points (A,B) such that : Tpic = A*TOT² + B*TOT+C+Tinit 7/17/2015 CEA DSM Dapnia Sédi Time reconstruction + walk correction • Resuts : – With 8 thresholds : error on Tpic ~ 300ps RMS – With 3 thresholds : error on Tpic ~ 800ps (sigma), even with our digitisation error. But: double pulse recognition difficult with 3 thresholds • Conclusion : – With TOT exact computation (error of 800ps) of arrival time – With thresholds, approximation of number of photons 7/17/2015 CEA DSM Dapnia Sédi Solution for TOT • Schémas 1 : Analogue Digital FPGA • Time coding •Data compression Zero suppression Charge and Time Simulation Test on Virtex V 500MHz 1ns 1ns + Simplicity : few components - Communication Discri – FPGA high frequency - Time precision : 1ns Fsampl ≥1 GHz 7/17/2015 CEA DSM Dapnia Sédi Solution for TOT • Schémas 2 : Analogue Digital Clock FPGA n • Time coding … … … • Data compression n Data Discri. Sampling Data in parallel + Synchronous + Communication Discri – FPGA medium frequency - Volume of simultaneous data … 7/17/2015 CEA DSM Dapnia Sédi Backup 7/17/2015 CEA DSM Dapnia Sédi VFE principle • Limited functionalities – – – – – – – Discriminate signals coming from the PMT. Measure their time (~ 0.5 ns rms precision). Measure their charge. Bufferize and Derandomize the event flow. Convert charge & time in digital data. Format the events & serialize them toward the DAQ board. An Oscilloscope mode (Wave Form) – – – Rate Monitor + rate alarm. Test Led generator. … • Discrimination principle • Electrical Shape from PMT, in case of single photon, is known : Only arrival time (T0) and charge is needed. • In order to recognize patterns from multi-muon bundles, TOT larger than T0+T1 is treated as a Waveform 7/17/2015 CEA DSM Dapnia Sédi Amplitude T0 + few ns T0 Charge WaveForm Threshold T0 T0 + T1 Time Résumé : Q > 10 PE 10 > Q > 2 Amplitude Amplitude Temps • Bonne approximation de la charge, quelque soit la méthode. CEA DSM Dapnia Sédi Amplitude Temps • Fit ne voit pas le 2e pulse • TOT surestime ou sousestime la charge • Géo. bonne approximation 7/17/2015 2>Q Temps • Fit et TOT: bonne approximation si pas de 2e pulse sous le 1er seuil • Géo. : pas d’interpolation possible Future developments • • Complete schematic simulations Scale Prototype : include in a new PMT readout scheme DAQ Board ARS Board – Board number reduction – Component number reduction System On Chip • 7/17/2015 VFE VFE PMT control TOT option under study CEA DSM Dapnia Sédi SoC Objectives : – VFE – Antares compatibility – Tests in laboratory – OM integration (in the sphere) – Test in situ