Transcript RF Modeling of Sub-100 nm CMOS - MOS-AK

RF Modeling of Sub-100 nm
CMOS
S.Yoshizaki1, M.Nakagawa1, W.Y.Chong1, Y.Nara2,
M.Yasuhira2*, F.Ohtsuka2, T.Arikado2**, K.Nakamura2,
K.Kakushima1, K.Tsutsui1 H.Aoki1, H.Iwai1
1
Tokyo Institute of Technology
2 Semiconductor Leading Edge Technologies, Inc. (Selete), Japan
* Current affiliation : Matsushita Electric Industrial Co., Ltd., Japan
** Current affiliation : Tokyo Electron Ltd., Japan
Background ~RF Technology~
Spread of the cellular phone and the
wireless LAN.


The age of Digital information appliances
RF technologies serve the rapidly
growing wireless communication markets.

Fig.1 4-th Generation mobile
 Center Research Laboratory,
Hitachi Ltd.
100%
Accurate RF Modeling become
important to more than before.
But …
80%
60%
40%
20%
0%
In RF, some parasitic
elements effect more severe.
2004
2005
2006
2007
2008
2009
Fig.2 Technology-development cost
reduction (due to TCAD)
 ITRS2004update, 2004
Feature in RFCMOS
Merit
Demerit
Low cost compared with
compound semiconductors
Low operation voltage with
scaling
Consolidation with logic
circuits
SN ratio degradation


Scaling and Circuit
technologies improve
fT and fmax
Fig.3 Application Spectrum
 ITRS2004, 2004
The concern about High-k
MOSFET in RF
① Degradation of dielectric constant with dielectric relaxation.
② RF characteristic deterioration with degrading mobility.
③ Increase interface state density → Increase Low-frequency
noise and thus Phase noise.
Motivation
RF Modeling of Sub-100 nm High-k MOSFET
► There
are little reports about RF
performance evaluation and modeling with
High-k MOSFETs.
► Comparison HfSiON with SiON.
Device
►
EOT = 1.5nm (HfSiON & SiON)
► Gate length
HfSiON (Lg= 64nm), SiON (Lg= 51nm)
► The number of finger = 12（W=5μm）
silicide
HfSiON
SiN
Si
G
Fig.4 HfSiON MOSFET structure
S
G
S
S
silicide
SiON
S
D
S
D
Si
M1
Fig.5 SiON MOSFET structure
G
VIA1
STI
SiN
S
63.9nm
G
D
61.7nm
G
S
G
D
62.3nm
65.5nm
Fig.6 Section of HfSiON MOSFET
G
S
65.3nm
Increase gate width with increasing number of
fingers, the gate resistance become small.
RG 
W
1
Rsh tot2
3
LN f
Nf : The number of finger
DC Measurement and Simulation
【HfSiON】
6.00E-04
Vgs=0, 0.6, 0.9, 1.2, 1.5V
Measured
5.00E-04
Simulated
3.00E-04
2.00E-04
1.00E-04
7.00E-04
0.00E+00
6.00E-04
0
0.5
1
Vd[V]
Fig.7 Measured and simulated Ids-Vds
【HfSiON】
1.5
5.00E-04
Id/W[A]
Id/W[A]
4.00E-04
4.00E-04
3.00E-04
2.00E-04
1.00E-04
0.00E+00
0
0.5
1
Vd[V]
Fig.8 Measured Ids-Vds 【SiON】
1.5
De-embedding
To de-embed parasitic elements including wires
and pads is important that could obtain the real
device parameters.
Cgd
Rgdp
OPEN
Drain
Ld
Gate
Gate
Drain
Gate
Drain
Rd
Cd
Lg
Rg
BSIM4
Cg
Rs
Rdp
Rgp
Ls
DUT
SHORT
Measured and Simulated fT, fmax
【HfSiON】
H21, GAmax[dB]
50
Measured GAmax
Simulated GAmax
Measured H21
Simulated H21
40
30
20
Vg=1.2V, Vd=1.5V
fT,HfSiON = 189.9[GHz]
10
fmax,HfSiON = 59.9[GHz]
0
LD
0.1
1
10
Frequency[GHz]
100
1000
CGD
Fig.9 H21 and GAmax vs. Frequency 【HfSiON】
gm
fT 
2CGS
f max
ft

2 ( g ds ( RG  RS )  2fT RG CGD )
Rg
RD
BSIM4
CGS
Fig.10 Equivalent circuit model
Measured S-parameter and
Predicted fT, fmax 【SiON】
60
Measured GAmax
Extrapolated GAmax
Measured H21
Extrapolated H21
H21, GAmax[dB]
50
40
Vg=1.2V, Vd=1.5V
30
20
fT,SiON = 236[GHz]
10
fmax,SiON = 74[GHz]
0
0.1
1
10
100
1000
Frequency[GHz]
Fig.11 H21 and GAmax vs. Frequency 【SiON】
RF Characterization
~ fT & gm Comparison HfSiON with SiON~
250
100
80
70
150
60
50
100
40
Cross SiON and
HfSiON characteristics
30
gm peak
50
20
10
0
0.01
0
0.1
1
Id[A]
Fig.12 fT and gm vs. Id
10
100
gm[mS]
200
fT[GHz]
90
fT【SiON】
fT【HfSiON】
gm【SiON】
gm【HfSiON】
300
300
250
250
200
200
fmax[GHz]
ft [G H z]
Position of this device
150
100
nmos
150
pmos
100
nmos
50
50
pmos
0
0
0.01
0.1
1
0.01
ゲート
長[μm[um]
]
Gate
Length
Gate
Length
ゲート
長[μm[um]
]
SiON
HfSiON
0.1
Fig.13 fT and fmax
 IEDM, VLSI 1995～2004
1
Summary
We measured and simulated High-k MOSFET RF
characteristics.

Measured from 500MHz to 40GHz, there is no dielectric
relaxation.

Simulated fT and fmax in HfSiON, we obtained good fT
(189.9GHz) relatively.

SiON is expected much more high performance than
HfSiON. I guess this is because of mobility degradation.

Acknowledgement
This work was partially supported by Special Coordination
Funds for Promoting Science and Technology by Ministry of
Education, Culture, Sports, Science and Technology, Japan.
Appendix A
~Flicker noise~
nmos
Sid[A^2/Hz]
1.00E-14
SiON
HfSiON
1.00E-15
1.00E-16
1.00E-17
1.00E-18
1.00E-19
0.01
0.1
1
10
Frequency[kHz]
100
Id=1mA / Vd=0.1V
Fig.14 Flicker noise
Appendix B
~RF CMOS Evaluation Equipment~
8 inch wafer, 40 GHz