Transcript RF Noise Models of MOSFETs

Analytical Modeling of
RF Noise in MOSFETs –
A Review
S. Asgaran and M. Jamal Deen
Electrical and Computer Engineering, CRL 226
McMaster University, Hamilton, ON L8S 4K1, Canada
[email protected]
RF Performance of MOSFETs
● DUTs are fabricated in 0.18mm CMOS technology and measured at
VDS = 1V
● Maximum fT is around 50 GHz and the best NFmin is about 0.5 dB at
2 GHz
2
Noise in MOSFETs
Io
+
VD
_
IDS
Io
Drain
Gate
Substrate (Body)
+
VG
_
Source
VG
L
VD
Gate
W
channel
noise
FT
time
induced gate noise
Source
e-
n+
gDS(x)v(x)
p-substrate
Drain
n+
E lateral field
1/f noise
white noise
channel noise
frequency
3
Why Does Noise Matter
Pout
(dB)
Burn out
ideal amplifier
saturation
10
0
-10
Power
dynamic
range
-20
-30
noise floor
-40
distance
-50
Distance
-60
-70
-80
-60
Pin1
-40
Pin2
-20
0
20
Pin (dB)
The battery life time and the distance between the wireless components will
be limited by the noise floor of the front-end amplifier.
4
Outline
● Introduction
● Noise sources
● RF MOSFET noise models: long and short
channel – only explicit analytical models
are discussed
● Induced gate noise
● Applications of models to design
● Conclusions
5
Introduction
● Why CMOS for
RF?
►Low cost
►High integration
►Integration with
digital IC (SoC)
►Technology
advancement
♦ higher frequencies
J.C. Rudell, J-J. Ou, T.B. Cho, G. Chien, F. Brianti, J.A. Weldon, P.R. Gray, A 1.9-GHz wideband IF double conversion CMOS receiver for cordless telephone applications IEEE Journal
of Solid-State Circuits, Vol. 32, pp. 2071-2088, Dec. 1997
6
Noise Sources in MOSFET
SvRG
G
RG
CGB
SiG
S
CGS
Im
CGD
RS
Ims
RD
SiRS
SiD
D
88%
SiRD
0.25mm technology
RDS
SiD ~ Lch-1
CBS
RSUB ~20% total Sin
RDSB
CBD
SiRDSB
RG ~5% total Sin
L=0.18 mm, f=3 GHz
SiRSB
RSB
RDB
SiRDB
B
B
C. Enz, An MOS transistor model for RF IC design valid in
all regions of operation IEEE Trans. Microwave Theory
Tech., Vol. 50, pp. 342-359, Jan. 2002.
● SiD: Channel noise + flicker noise
●SiG: Induced gate noise
● SiR: Thermal noise of real resistances
A.J. Scholten et al, Noise modeling for RF
CMOS circuit simulation, IEEE Trans. Electron
Devices, Vol. 50, pp. 618- 632, Mar. 2003.
SID 
4kT
VDS
2
 g (V ) dV 
I D L2elec VSB
1
Lelec
~20% discrepancy for 0.18mm, low f
SiD increases with f in 2mm FET
No dependence on VDS in saturation
7
Noise Models- Long Channel Case
● Klaassen-Prins:
S iD
4kT
 2
L ID

S iD
4kT
 2
L ID
VDS
S iD
4kT m

Qinv
2
L
►Integrating the noise
current over the entire
channel
● Van der ziel:
►Includes hot electron
effects
►Te: a function of E(x)
● Tsividis:
►Simpler model
VDS
0

0
g 2 (V0 )dV0
Te ( x) 2
g (V0 )dV0
T
8
Noise Models - Short Channel
iD (Amp/Hz1/2)
20
G
VGS=0.7, 0.9, 1.1, 1.3, 1.9V
16
VDS=2.5V
12
S
8
(II)
Lsat,VDSat
4
0
(I)
0
2
4
6
8
10
Channel Length (mm)
P. Klein, An analytical thermal noise model of deep
submicron MOSFET’s, IEEE Electron Dev. Letters,
Vol. 20, pp. 399-401, Aug. 1998.
12
SiD  4kT
● Increased noise in short channel devices
● A divided channel is used
D
L
Leff,VDS
meff QI
L2
I DS
8
 qvsat e
3
L
vsat~107cm/s
~4.3ps
SID ~ indep. of VDS
► Linear region (GCA)
► Velocity saturation region; thermal assumption questionable
9
Triantis et al
2
● SiD  g DS
 SV 1  SV 2  is
questionable! gDS is not
constant
● Te: in both parts of the
channel
● rD  EII ( x)x / I D thermal
noise source in vel. sat.
region: questionable! rD
is an ac resistance
● Old measurements (Abidi,
‘86) used
● SID ~ indep. of VDS (< 1.5x)
Drain Current Noise (Amp2/Hz)
RF MOSFET Noise Models
10-21
Total noise
Measurement
Region I
noise
10-22
Region II
noise
10-23
VDS=4V
W=30mm; L=0.7mm
10-24
0
1
2
3
4
5
6
VGS (V)
D.P. Triantis, A.N. Birbas and D. Kondis, Thermal
noise modeling for short-channnel MOSFET’s,
IEEE Trans. Electron Devices, Vol. 43, no. 11,
pp.1950-1955, Nov. 1996.
Note: Region II noise increases with
VGS; device is less saturated
Note: Calculations > measurements
10
RF MOSFET Noise Models
● Mobility degradation due to
channel field absent
● Carrier temperature, Te,
used to model hot carrier
effects
● Noise of VS region:
intrinsic diffusion noise
● SiD=g2DS×(SvI+SvII) questionable!
● Measurements (Abidi, ‘86)
●
2

 E ( x)  

Temp: Te ( x)  To 1  d 

EC  



● d~5-20 for EC=2-4V/mm
Drain Current Noise (Amp2/Hz)
Park and Park
10-21
Total noise - Triantis
Park & Park
Measurement
Region II noise
Park & Park
10-22
Region I noise
Triantis
Region I noise
Park & Park
10-23
VDS=4V
Region II noise
Triantis
10-24
1
2
5
4
3
VGS (V)
SiD
C.H. Park and Y.J. Park, Modeling of thermal noise
in short-channel MOSFETs at saturation, Solid-State
Electronics, Vol. 44, pp. 2053-2057, 2000.
 4kTV
2 
c
 g DS 
 I D
2
  2 VC2 - VGTVC  VGT

3

d 
2
(VGT - VC )


cosh ( Lsat / l ) 
2

3 
L
sat 
3 s2W 2 x 2j vs3

4qDID
11
RF MOSFET Noise Models
Knoblinger et al
● Te: in both parts of channel
E ( x) 2
● Te: Te  T  d T 2
Ec
● meff=v(x)/E(x) in both parts
of the channel: wrong!
SiD 
4kT
4kTI D
m eff Qinv  d
V
2
2 2 DS
L
L Ec
G. Knoblinger, P. Klein & H. Tiebout, A new
model for thermal channel noise of deepsubmicron MOSFETs and its application in RFCMOS design , IEEE J. Solid-State Cir., vol.
36, pp. 831-7, May 2001.
4kTI D 2
arctanexp(L) - arctan(1)

2

L Ec
d
4kTI D 1
sinh(L)
2

L Ec
G
S
(I)
Lsat,VDSat
(II)
L
Leff,VDS
D
d~1.0 and noise from region Ia
(T=lattice temperature) gave
better fit to data at VGS>1.5V
12
RF MOSFET Noise Models
Scholten et al
● CLM not taken into
account
1
S iD  2
L ID
m
VDSat

0
4kTe ( x) g 2 (V )dV
m eff
  E
1  
  EC



p



1
p

E 

Te  T 1 
EC 

Te is not needed!
n
A.J. Scholten et al, Accurate thermal
noise model for deep-submicron CMOS,
IEDM Tech. Digest, pp. 155-158, 1999.
13
RF MOSFET Noise Models
Chen & Deen
● Channel length
modulation (CLM) is
accounted for
● d=0 in experiments
► no Te needed
● No noise from VS
region
S iD 
4kTm eff
L2elec
Qinv
4kTI D
d 2
VDSat
2
Lelec EC
C.H. Chen and M.J. Deen, Channel noise
modeling of deep submicron MOSFETs,
IEEE Trans. Electron Devices, vol. 49, pp.
1484-1487, Aug. 2002.
14
RF MOSFET Noise Models
Scholten et al
●
●
●
●
Modified Klaassen-Prins
Takes into account CLM
No noise from VS region
A closed-form solution as a
function of surface potential
- too complicated! Difficult
to provide insight to
designers
● Not accurate for short
channels at high VGS
S iD
4kT
 2
Lelec I D
VDS

0
g 2 (V0 )dV0
A.J. Scholten et al, Noise modeling for RF
CMOS circuit simulation, IEEE Trans.
Electron Devices, Vol. 50, pp. 618- 632, Mar.
2003.
Si D 
1
L el ec
15
RF MOSFET Noise Models
Han et al.
● Considers the channel
field effect on mobility
● Starts from impedance
field theory
● Uses Einstein equation
in MOSFET channel :
questionable! MOSFET
channel is degenerate in
strong inversion
● The result is based on
thermal noise theory
d in2  4qfDn Qinv
SiD 

E
2

g
(
V
)
1

 o
 E
0
c

VDS
4kT

VDS 

L2elecI D 1 
LelecEc 

W
x
2

dV

K. Han, H.Shin and K. Lee, Analytical Drain Thermal Noise Current Model Valid for Deep Submicron
MOSFETs, IEEE Trans. Electron Devices, vol. 51, pp. 261-269, Feb. 2004.
16
RF MOSFET Noise Models
SiD 
4kT

L2elecI D 1 
VDS 

LelecEc 
2


E 
2
dV
 g o (V )1 
0
 Ec 
VDS
Dashed line
is without this
term
K. Han, H.Shin and K. Lee, Analytical Drain Thermal Noise Current Model Valid for Deep Submicron
MOSFETs, IEEE Trans. Electron Devices, vol. 51, pp. 261-269, Feb. 2004.
17
RF MOSFET Noise Models
G
Analytical Model
● Based on simple
S
analytical drain current
expression
● Includes the channel
field effect
● Suitable for circuit design
(II)
Lelec
L
D
Leff,VDS
Lelec 
● Purely analytical (no
integration, etc.)
(I)
S iD
VGT (VGT - V0 )
and V0  I D
WC ox vsat
EcV0
4VGT2  V02 - 2V0VGT
 4kTI D
3VGT2 (VGT - V0 )
2
 1
 dID 
dSiD

V
dsat

 4kT 


2


dV SB
3VVT  dV SB 
 Vdsat
with VSBopt  Vdsat - S
18
RF MOSFET Noise Models
SiD 
4kT m eff
L2eff
Qinv
model
Analytical model
Analytical model
B. Wang, J.R. Hellums and C.G. Sodini, MOSFET thermal noise modeling for analog
integrated circuits, IEEE JSSC vol. 29, pp. 833-835, July 1994.
19
RF MOSFET Noise Models
● Noise and scaling
 1
SiD  4kTW v V 
sat GT E L
 c c



2
3 (Ec Lc  VGT ) 
2
Ec Lc
● For very short
channel devices
VGT
1
S iD  4kTW Cox m eff

2
Lc
20
Induced Gate Noise
● Induced gate noise at x in channel
id(xo)
CGS
j WLCox  g (Vo )v( xo )
ig ( xo ) 

Vas - V ( xo )
I ds
Lelec
where
Vas  VDS -
1
2
VGS - VTH VDS -16 VD2S
VGS - VTH - 12 VDS
● Induced gate noise ig(xo) is fully correlated with the
channel thermal noise id (xo)
● VDS becomes VDSsat in the saturation mode
21
SIG and Correlation Noise
SiG (A2/Hz)
L=0.64 mm
L=0.42 mm
1×10-23
L=0.27 mm
L=0.18 mm
1×10-24
8×10-23
Correlation Noise (A2/Hz)
L=0.97 mm
1×10-22
L=0.97 mm
6×10-23
L=0.64 mm
4×10-23
L=0.42 mm
2×10-23
L=0.27 mm
L=0.18 mm
0
1×10-25
1
Frequency (GHz)
10
1
2
4
5
3
Frequency (GHz)
6
● MOSFET channel- RC network at high f
► Gate capacitance and channel R
● Channel noise coupled to the gate→ SIG, correlation noise
● Frequency dependent
● Negligible as the channel length shrinks
M.J. Deen, C.H. Chen and Y. Cheng, MOSFET Modeling for Low Noise, RF Circuit Design,
Proceedings of IEEE CICC, pp. 201-208, May 2002
22
Choosing Device Size
NFmin
gm,max
● Channel length of devices reduced
► Increased gm and peak value of gm occurs at lower VGS values
● The faster increase in gm results in
► Reduced NFmin and the lowest NFmin is shifted to lower VGS values
23
Choosing DC Bias Conditions
gm
NFmin
● Higher VDS bias will increase gm at the higher VGS region
● Higher gm will decrease NFmin at higher VGS region
● Decreased NFmin at higher VGS makes lowest NFmin less sensitive to VGS
24
Concluding Remarks
● MOSFET channel noise analytical models
discussed
► Long channel case
► Short channel case
● Some ideas on how to use noise to design
circuits
● Future applications demand low power
► MOSFET in moderate or weak inversion
► Noise models needed in these regions
25
Acknowledgements
● Professor C.H. Chen (McMaster University)
● Dr. Y. Cheng (Conexant/Skyworks)
● Funding - Rockwell/Conexant/Skyworks, USA
and Gennum, Canada
● Funding - NSERC of Canada
● Funding - Micronet
● Funding - Canada Research Chair Program
26