Transcript 슬라이드 1 - DDTek

Design Database Checklist – (Ⅰ)
Checked by :
Date : 20
,
,
1.PRE Notice Information
2) Wafer size : (
1) Customer Device Name :
) Cheongju F2-6” , (
3) Fab Site : (
) Gumi F3-8” , (
4) Application *1) :
) 6”
, (
) 8”
) Cheongju F4-8”
5) Device *2) :
6) Poly / Metal Layer : (
) Poly / (
) Metal
7) Multi-Chip(Yes/No) : (
) Yes , (
) No
8) Please confirm database
(
) New Database (
) Full Revision (
) Partial Revision (Rev. reason :
)
Privious Device Name :
9) DB Transfer Date :
10) Product Type : (
11) FTP account ID (
)
12) How many wafers need to be input?
Input Q’ty (
) Fab out Q’ty (
)
) Wafer , (
Ship to (
)
Hold Q’ty (
) & Hold Step (
2. Database Transfer Information
1) Mask P.O. # :
2) Requested Delivery Date :
3) DB File name & size
:
DB File Size(byte) :
Top Structure
:
Description
:
3. Customer Information
1) Company Name :
2) Business Contact Point
Name
3) Engineering Contact Point
:
Name
:
Telephone :
Telephone :
E-mail
E-mail
:
:
4. MagnaChip Information
1) Business Contact Point
AM
2) Engineering Contact Point
:
Name
:
Field Sales :
Telephone :
Field CE
E-mail
:
:
5. Product Information
1) Target Process :
2) Frequency & Temp : (
) MHz , (
)℃
~
3) Operating Voltage
Logic
: Core(
High Voltage : Drain(
) V , I/O (
) V , Gate (
)V
) V , I/O (
4) Is this already in production at other (1st) Foundry? (
)V
) Yes (
5) Package Type :
Taegee Co., Ltd.
Taegee
Design-driven Foundry
Samheung Bldg 705-9 Yeoksam-Dong
Gangnam-Gu Seoul, Korea 135-711
Tel: 02-555-2583 Fax: 02-555-2584
www.taegee.co.kr
(
)
(If you already have an account for DB transfer, please fill it in.)
13)If you have additional Instruction, please describe it.
DB File Name
) Others
-1-
) No
1st Foundry :
)
Design Database Checklist – (Ⅱ)
6. Chip Design Information
1) Is your product original version or shrink version?
2) Did you use MagnaChip library? (
(
) Original Version
) MagnaChip Library
(
(
) Shrink Version
) Full Custom
If Yes, What is the library name? :
3) Is this product designed for MagnaChip process?
If yes, fill in the name and version of documents.
Logic
High Voltage
Design Rule #
:
Spice Parameter #
:
Electrical Parameter #
:
Design Rule #
:
Spice Parameter #
:
Electrical Parameter #
:
4) Are there Special Blocks?
(
) Yes
(
(
) Yes
(
) No
) No
Memory Type :
Memory Size :
Analog Block :
* If Flat ROM / OTP / Mask ROM case, please describe application in detail :
* In case of Flat ROM / OTP / Mask ROM (Over 4M bit), customer should release body and all code D/B to MagnaChip.
These body and code D/B can be verified by 3rd party.
5) What IPs did you use in your product?
Used IP & Provider :
Qualified or Not
:
6) MagnaChip has to merge 3rd party IP into main DB?
IP Types (ex. OTP)
(
) Yes
(
) No
:
7. Option Process Requirement
1) EPI wafer
:
(
) Yes
(
) No
If yes, please attach the EPI wafer spec (
2) Polyimide
:
(
) Yes
(
) No
If yes, please specify target thickness
(
)um
3) Thick Metal :
(
) Yes
(
) No
If yes, please specify target thickness
(
)um
4) Deep Nwell :
(
) Yes
(
) No
5) Back grinding :
(
) Yes
(
) No
If yes, please specify size (
6) Blocking gate poly used? :
(
) Yes
(
) No
Generated by?
(
) Customer
) File Upload
)um
(
) MagnaChip
-In case of 1st poly as a resistor (For instance: Optional resistor poly), it means that the blocking poly as Gate Poly (2nd Poly)
covers the 1st poly resistor on the resistor area to reduce the variation of thickness caused by the following process.
- If Blocking gate poly is used, specify required non-salicided Cpoly resistance (
Ohms/sq )
7) Fuse Pattern used? :
(
) Yes
-If Yes, what’s the fuse layer? (
(
) No
)
8) Special Process :
Taegee Co., Ltd.
Taegee
Design-driven Foundry
Samheung Bldg 705-9 Yeoksam-Dong
Gangnam-Gu Seoul, Korea 135-711
Tel: 02-555-2583 Fax: 02-555-2584
www.taegee.co.kr
-2-
Design Database Checklist – (Ⅲ)
8. Device Parameter Target
1) Designed for MagnaChip's standard parameter ?
(
) Yes
(
) No
(
) Yes
(
) No
If no, please supply the device parameter target used :
2) Do you need Special Device & Target Specification?
Resistor
(ohm/sq)
N-Poly : (
) Ω /sq
P-Poly : (
) Ω /sq
C-Poly : (
) Ω /sq
N-Well : (
) Ω /sq
BJT
(
) Yes
(
) No
N-Diff. : (
) Ω /sq
Zener Diode
(
) Yes
(
) No
P-Diff. : (
) Ω /sq
Option Transistor
(
) Yes
(
) No
High R : (
) Ω /sq
Capacitor
(fF/um^2)
PIP
(
) fF/um^2
MM
(
Metal (
) fF/um^2
) ~ Metal (
)
9. Special Instructions
1) Corner/ Engineering split conditions required?
(
) Yes
(
) No
If yes, please attach file :
File UPLOAD
If yes, please describe it :
2) What is the Scribe Lane Width?
(
) 100um
(
) 80um
(
) Others (
um)
3) Mask Combination.
If you need mask combination, please describe it on the table below.
1. (
)
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)
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)
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42. (
)
* Revision Layer Name (If yes) :
* Special layer Code Layer Name (If yes) :
Option Layer Name (If yes) :
Base Array Hold Step: (
) (If you are using a special layer(s), please input base array hold step.)
4) If you have additional Instructions or files, please describe or attach them.
*1) Consumer
Data Processing
Wireless
Wired
Auto Motive
Industrial
Other
: Digital TV/ MP3/ DVD ..
: Note Book/Desktop/Monitor…
: Mobile Phone/Wireless LAN….
: LAN Card/Router/Modem….
: Telematics /GPS/Sensor…
: Semiconductor manufacture / Test ….
: Direct Input
*2) Analog
Display Driver
Micro controller
Power Management
MEMS
Others
Others
Taegee Co., Ltd.
Taegee
Design-driven Foundry
Samheung Bldg 705-9 Yeoksam-Dong
Gangnam-Gu Seoul, Korea 135-711
Tel: 02-555-2583 Fax: 02-555-2584
www.taegee.co.kr
-3-
Attach File
: Amplifier/ADC/DAC….
: OLED Driver/Source Driver….
: 4,8Bit MCU/OTP…..
: LDO/Battery Management…
: Microphone/Gyroscope….
: RFID/EEPROM/CIS
: Direct Input
CAD Database Information – (Ⅰ)
DB File Name :
Top Structure :
File Size :
Window Size
CAD Database Window Coordinates
Format
X=(
Y=(
)
)
X-LB (
)
Y-LB (
)
X-RT (
)
Y-RT (
)
GDS II
X=(
Y=(
)
)
X-LB (
)
Y-LB (
)
X-RT (
)
Y-RT (
)
MEBES
1) Shrink & Rotation
DATA SHRINKAGE : TO (
DATA SHRINKAGE : TO (
DATA SHRINKAGE : TO (
)%
)%
)%
2) If MagnaChip's design Rule is not used, please supply the used Design Rule.
Customer has completed DRC check :
(
) Yes
(
) No
Using MagnaChip command file :
(
) Yes
(
) No
If yes, please confirm :
(
) Pass
(
) Fail
3) Customer add OPC pattern :
(
) Yes
4) Customer add dummy layer fo poly : (
(If using MagnaChip 0.35um lib.)
) Yes
5) Customer added seal ring structure :
if yes, please confirm : MagnaChip rule(
(
6) Need customer Test-pattern :
(
(
(
Attach DRC summay file.
) No If yes, specify layer name. :
) No If yes, specify layer name. :
) Yes
(
) No
) Put customer's own seal ring (
) Yes
(
)
) No If yes, specify Test-pattern name. :
7) Customer Job Deck View : ( if yes, please confirm )
( ) Yes
( ) No
( ) Start mask making after JD confirmed ( ) Start mask making & JD in parallel
( ) Customer Site ( ) Magna Chip Site ( ) Mask Shop Office
8) Customer assign MASK vendor : (
) Yes
(
) No If yes, please fill in mask vendor name :
GDS II DATA DESCRIPTION
Layer #
Layer
Descript
D.A.Tone
Min. GRID
MEBES DATA DESCRIPTION
Contact &
Via Size
Pattern
File Name
Taegee Co., Ltd.
Taegee
Design-driven Foundry
Samheung Bldg 705-9 Yeoksam-Dong
Gangnam-Gu Seoul, Korea 135-711
Tel: 02-555-2583 Fax: 02-555-2584
www.taegee.co.kr
-4-
Layer
Descript
Trapezoid
Spot Size
Scale
1X / 5X
CAD Database Information – (Ⅱ)
GDS II DATA DESCRIPTION
Layer #
Layer
Descript
D.A.Tone
Min. GRID
MEBES DATA DESCRIPTION
Contact &
Via Size
Pattern
File Name
Layer
Descript
Trapezoid
Spot Size
Additional Instructions :
If you have additional question , please contact [email protected] or [email protected] Tel : 02 – 555 - 2583
Taegee Co., Ltd.
Taegee
Design-driven Foundry
Samheung Bldg 705-9 Yeoksam-Dong
Gangnam-Gu Seoul, Korea 135-711
Tel: 02-555-2583 Fax: 02-555-2584
www.taegee.co.kr
-5-
Scale
1X / 5X