Transcript MODERN presentation template

MODERN 1st Year Review
ENIAC-120003 MODERN
Ref. Technical Annex MODERN_PartB Rev2 v2.4
WP1: Giuliana Gangemi
WP3: Wilmar Heuvelman
WP5: Loris Vendrame
Coordinator: Jan van Gerwen
Date: June 22, 2010 (09.30 - 17.00 hrs)
Review period: 2009-03-01 : 2010-02-28
WP2: André Juge
WP4: Davide Pandini
Agenda
General information (JvG)
–
–
–
–
–
–
–
Objectives
Consortium
Resources planned and used
Overview of deliverables and milestones status
Cooperation, dissemination and exploitation
Project management: progress, funding problems and amendments
Other issues, Q&A
For WP1 (GG), WP2 (AJ), WP3 (WH), WP4 (DP) and WP5 (LV)
–
–
–
–
–
–
Relationship between workpackages
Progress, highlights and lowlights
Technical status and achievements of deliverables (incl. changes)
Cooperation
Dissemination (publications, patents), exploitation
Other issues, Q&A
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 2
Objectives
The objective of the MODERN project is to develop new paradigms in
integrated circuit design that will enable the manufacturing of reliable,
low cost, low EMI, high-yield complex products using unreliable and
variable devices.
Specifically, the main goals of the project are:
 Advanced, yet accurate, models of process variations for
nanometre devices, circuits and complex architectures.
 Effective methods for evaluating the impact of process
variations on manufacturability, design reliability and circuit
performance.
o Reliability, noise, EMC/EMI.
o Timing, power and yield.
 Design methods and tools to mitigate or tolerate the effects of
process variations on those quantities applicable at the device,
circuit and architectural levels.
 Validation of the modelling and design methods and tools on a
variety of silicon demonstrators.
1
2
3 4
Layout and strain induced variability (Synopsys)
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 3
5
Consortium
The MODERN Consortium features strong competence and expertise
in the field of advanced technologies, with a well-balanced participation
between Large Industries, SMEs, Research Centres and Universities
from all over Europe.
28 Partners
9 Countries
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 4
WP3
WP4
WP5
WP6
9
6
0
58
107
56
0
639
198
137
0
730
169
77
0
603
52
38
0
274
29
18
0
115
563
331
0
2,419
5
6
5
19
0
0
66
18
20
54
84
7
7
60
16
15
44
0
12
9
9
36
24
36
12
6
0
0
0
66
19
55
78
16
15
14
1
0
2
63
2
2
0
5
13
0
0
43
5
0
0
0
73
6
14
0
0
42
5
9
33
9
32
0
0
12 109
2
19
0
0
56
18
20
0
84
6
55
0
0
84
6
0
0
0
66
2
2
6
12
13
6
17
16
48
70
68
30
7
18
18
13
12
12
24
14
14
18 204
5
6
66 102
15
36
3
3
30
30
3
2
36
18
18
6
1
1
54
12
10
48
24
28. University of Calabria
27. Alma Mater Studiorum
26. Vienna University
25. Graz University
24. Eindhoven University
23. Delft University
22. TIEMPO SAS
21. Thales SA
6
23
27
20
6
12
12
32
19
4
6
8
108
18
23
8
15
19
24
0
60
0
58
0
0
10
0
18
2
12
0
0
3
5
0
0
36
6
19
0
0
90
2
19
19
24
0
0
0
72 108
72
2
6
30
12
27
31 119
40
0
27
32 114
0
0
0
0
0
0
0
56 108 342 120 288
12 174
15
15
12
23
42
0
0
6
38
1
4
6
0
18
'(*) NOT FUNDED IN ITALY
MODERN 1st Year Review
June 22, 2010
7
7
6
4
42
6
6
2
27
27
0
95
18
18
2
12
12
1
1
29. The University of Glasgow
20. Synopsys Switzerland LLC
19. STMicroelectronics S.r.l.
18. Politecnico di Torino
16. (Coordinator) NXP-NL
4
4
24
5
5
19
1
1
0
15. Numonyx Italy Srl
13. Montpellier Laboratory
12. CEA-LETI
11. Consorzio Nazionale
9. STMicroelectronics SAS
8. IMEP-LAHC Laboratory
6. Infineon Technologies
5. Teklatech
4. Elastix
3. CSEM
2. AustriaMicrosystems AG
1
31. Universitat Politecnica de Catalunya
WP2
Actual total
Target
Planned total
technologies,
Cum. Act. total
application
Cum.Plan total
dom ains,
Actual total
Process/device
Planned total
to com pact
Cum. Act. total
m odeling
Cum.Plan total
Actual total
Physical/circuit
Planned total
to RT-level: PVaw are and PV- Cum. Act. total
Cum.Plan total
robust
Actual total
Architectural to
Planned total
system level:
Cum. Act. total
m odeling,
analysis, and Cum.Plan total
Actual total
Test structures
Planned total
and
dem onstrators Cum. Act. total
Cum.Plan total
Actual total
Managem ent,
Planned total
dissem ination
and exploitation Cum. Act. total
Cum.Plan total
Actual total
Plan total
TOTAL
Cum. Act. total
Cum. Plan total
Partner - Person-month per Workpackage
30. Sapienza Universita de Roma
WP1
Title
TOTALS
W
o
r
k
P
a
c
k
a
g
e
1. STMicroelectranics SA
TABLE 3. PERSON-MONTH STATUS TABLE
CONTRACT N°: 120003
ACRONYM: MODERN
PERIOD: m1 to m12
10. Integrated System Development SA
Resources planned and used
CONFIDENTIAL 5
12
0
0
70
0
0
0
0
4
17
0
0
50
3
3
30
0
0
0
0
0
30 186
1
1
16
2
2
3
19
19
0
30
6
15
21
0
84
Overview of deliverables and milestones status (1)
Del. no. Deliverable name
D1.1
Definitions of problems and technologies,
Specifications for tools, methods and design techniques
1
ST-I
R
PP
Delivery
date
(proj.
month)
M06
D1.2
Check list and verification tests for tools, methods and design
techniques
1
ST-I
R
PP
M12
D2.2.1
Assessment of state-of-the-art TCAD methodology and
usability concerning PV for industrial purposes including
identification of current deficiencies of tools
Device simulation analysis of dominant variability sources in
45nm planar bulk CMOS technologies. Prototype
implementation of the treatment of individual dopants and
traps in the device modelling tools
Characterization of the influence of variability sources in
planar bulk CMOS devices down to 45nm.
Experimental characterization of Non-Volatile- Memory
devices in the presence of PV.
Parametric mismatch fluctuation effects in 32 nm FinFETs,
first PV results on 22nm FDSOI MOSFETS
Specification of considered degradation effects, modelling
approaches and device parameters
Set of alternative symbolic models for lib cells
2
UNGL
R
CO
M06
2
UNGL
R
CO
M12
UNGL, UNET,
ST-I, SNPS
26-02-2010
Yes
2
NXP
R
CO
M12
STF2, IMEP,
UNET, NXP
NMX, LETI,
UNGL
29-03-2010
Yes
2
AMS
R
CO
M06
UNGL, TUW
09-09-2009
Yes
3
TUD
P
CO
M12
23-04-2010
Yes
D3.2.1
Process development kit (PDK), circuit techniques, and speedup algorithms for PV-aware circuit simulation
3
UNBO
R
CO
M12
NXP, ST-I,
TUD, TUE,
UNRM
ST-I, UNBO,
UNCA, UNRM
02-04-2010
Yes
D3.3.1
PV-tolerant schematics evaluation and Monitor & Control
(M&C) strategies in digital and AMS&RF
3
POLI
R
CO
M12
CSEM, IFXA,
LETI, POLI,
UPC
29-03-2010
Yes
D2.2.2
D2.3.1
D2.4.1
D3.1.1
WP no.
Task
lead
Nature Dissemina
tion
level
MODERN 1st Year Review
June 22, 2010
Contributors
(lead)
Actual /
Forecast
delivery date
ST-I, AMS,
IFXA, NMX,
NXP, THL
15-06-2010
No
Postponed
ST-I, AMS,
IFXA, NMX,
NXP, THL
UNGL
31-07-2010
No
Postponed
10-09-2009
Yes
CONFIDENTIAL 6
Delivered Comments
Overview of deliverables and milestones status (2)
Del. no. Deliverable name
WP no.
Task
lead
Impact of supply noise, and clock distribution on EMI and
circuit timing
RF-interaction models for combined PCB-package-IC
PV-tolerant asynchronous blocks, ultra low-power circuits and
architectures, and asynchronous/de-synchronization flow
3
NXP
R
CO
Delivery
date
(proj.
month)
M12
3
4
NXP
ELX
R
R
CO
CO
M12
M12
D4.3.1
Robust architecture specification and SystemC model
4
ISD
R
CO
M12
D5.1.1
Review of test structure state of the art and first results on
intra-die variability and matching characterization on available
structures in different technology nodes
Basic concept verification of on-chip monitor, noise,
compensation, test chip architectures
Software prototype implementation of MOR for MIMO
systems of R, RC, RCL
Internal project website
IPR management guidelines
Risk management plan
Semi-annual project progress report
Project activity report (Year 1)
Public part of project web-site
Press release at the start of the project
5
AMS
R
CO
M12
5
IFXA
R
CO
5
SNPS
R
6
6
6
6
6
6
6
NXP
NXP
NXP
NXP
NXP
UNET
UNET
P
R
R
R
R
D
R
D3.4.1
D3.4.2
D4.2.1
D5.2.1
D5.3.1
D6.1.1
D6.1.2
D6.1.3
D6.1.4
D6.1.5
D6.2.1
D6.2.2
Nature Dissemina
tion
level
Contributors
(lead)
Actual /
Forecast
delivery date
Delivered Comments
LIRM, ST-I
16-04-2010
Yes
NXP
TMPO, CSEM,
ELX, POLI, STI
THL, ST-F,
ISD
NMX, STF2,
TUGI
02-04-2010
15-02-2010
Yes
Yes
01-02-2010
Yes
28-02-2010
Yes
M12
NXP, IFXA
25-03-2010
Yes
CO
M12
NXP
01-04-2010
Yes
CO
CO
CO
CO
CO
PU
PU
M01
M01
M06
M06
M12
M01
M03
ST-I
NXP
NXP
NXP, all
NXP, all
ST-I
ST-I
01-06-2009
01-10-2009
09-10-2009
04-12-2009
17-05-2010
01-06-2009
04-09-2009
Yes
Yes
Yes
Yes
Yes
Yes
Yes
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 7
Overview of deliverables and milestones status (3)
Milestone Milestone name
number
M1.1
M3.1
Problem Definition and Tests
Abstract Models CMOS and AMS&RF
Work
package(s)
involved
1,2,3,4,5
3
M3.3
PV aware circuit simulation techniques
3
M12
M3.5
M&C strategies for digital and AMS&RF
3
M3.7
RF interaction models
M4.1
PV-tolerant asynchronous/de-synchronized, ultra low-power, robust
functional blocks, and SystemC models
Prototype asynchronous/de-synchronization flow
First project review by ENIAC
M4.2
M6.1
Expected
date (proj.
month)
M12
M12
Actual /
Forecast
delivery date
31-07-2010
22-04-2010
Achieved Means of verification
Comments
No
Yes
Postponed
D 1.1, D1.2
Abstract models for CMOS cell
libraries reported and verified
02-04-2010
Yes
PV aware circuit simulation
techniques working and verified
M12
29-03-2010
Yes
3
M12
02-04-2010
Yes
4
M10
15-02-2010
Yes
4
all
M10
M08
15-02-2010
22-06-2010
Yes
No
M&C strategies for digital and
AMS&RF developed and
verified
RF interaction models
developed
D4.2.1
D4.3.1
D4.2.1
Reviewer’s feedback
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 8
Planned 22-06-2010
Cooperation, dissemination and exploitation
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 9
Project management: progress, funding problems
and amendments
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 10
Other issues Q&A
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 11
WP1: Relationship between workpackages
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 12
WP1: Progress, highlights and lowlights
Task T1.x: Task name
Partners (underlined task leader):
Explain in a few words: goal of task, what you did this period, what will be
delivered and when.
Explain in a few words: what went well, better than expected and what went worse
than expected; describe corrective actions.
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 13
WP1: Technical status and achievements of
deliverables (incl. changes)
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 14
WP1: Cooperation
WP leader: ST-I
If strong dependence on partners: list partners, describe dependence
Collaboration with partners: list partners, collaboration (division of labor, role, …)
Face to face meetings with: list partners (when)
Telephone conferences with: list partners (when)
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 15
WP1: Dissemination (publications, patents), exploitation
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 16
WP1: Other issues, Q&A
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 17
WP2: Relationship between workpackages
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 18
WP2: Progress, high- and lowlights
Task T2.x: Task name
Partners (underlined task leader):
Explain in a few words: goal of task, what you did this period, what will be
delivered and when.
Explain in a few words: what went well, better than expected and what went worse
than expected; describe corrective actions.
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 19
WP2: Technical status and achievements of
deliverables (incl. changes)
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 20
WP2: Cooperation
WP leader: STF2
If strong dependence on partners: list partners, describe dependence
Collaboration with partners: list partners, collaboration (division of labor, role, …)
Face to face meetings with: list partners (when)
Telephone conferences with: list partners (when)
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 21
WP2: Dissemination (publications, patents), exploitation
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 22
WP2: Other issues, Q&A
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 23
WP3: Relationship between workpackages
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 24
WP3: Physical/circuit to RT-level
Objective
– PV-aware and PV-robust circuit design techniques and tools, enabling the
design of reliable, low cost, low power, low EMI digital and AMS&RF
products
Tasks:
1. PV-aware circuit models
2. Methodologies, tools and flows for manufacturability, testability, reliability
and yield
3. PV-aware design
4. Design for low noise and EMI/EMC
Progress:
– The activity is on track, and planned deliverables were delivered
– milestones are on track
– A number of scientific papers were published in 2009
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 25
WP3: Progress, high- and lowlights
Task T3.1: PV-aware circuit models
Partners: TUD, LIRM, NXP, ST-I, TUE, UNRM
Process variation will be included in existing physical and symbolic circuit models. These
models are essential to effectively predict delay variations in order to be able to design
reliable and predictable electronic circuits.
D3.1.1NXP, ST-I, TUD, TUE, UNRM:
Set of alternative symbolic models for lib cells
Highlights
–
–
–
statistical standard cell model based upon statistical transistor models
algorithms to create a transistor-level simulator
Statistical analysis resulted in:
•
•
•
–
–
there are four different groups of paths from STA vs SPICE analysis
a novel statistical method has been developed for outlier identification,
a linear mixed model has been developed by taking the random and fixed effects into account for
predicting the delay of a path.
Build of VHDL delay models for standard cells which depend on technology parameters, allowing
Monte Carlo analysis of variability in delay already at the logic level
Verilog-A models which account also for process, design and operation parameters
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 26
T3.1 TUD&TUE&NXP: TL Statistical Standard Cell
Models for STA
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 27
T3.1 TUD&TUE&NXP: TL Statistical Standard Cell
Models for STA
Variance Components
• Lot (batch)
• Wafer
• Chips (110 ICs)
• Path (2269x110=249590 paths)
Analogous decomposition is standard in SPC applications
(e.g., thickness of oxide layers on chips)
16
Linear Mixed Model
Delayij      Lengthij  uj  ij
    Lengthij
for pathi on chip j
•
Path ID level
1. Linear effect of number of logic cells
•
Chip (IC) level
1. Position on the wafer
2. Production error
•
Path ID level
1. Type of logic cell (library)
2. Other properties (e.g., Flip-Flop)
Path level
1. Production error
2. Measurement error
•
17
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 28
T3.1 UNRM: VHDL Cell delay models
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 29
T3.1 STI: Analogue Circuit Models
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 30
WP3: Progress, high- and lowlights
Task T3.2: Methodologies, tools and flows for manufacturability, testability,
reliability and yield
Partners: UNBO, NMX, NXP, ST-I, UNCA, UNGL, UNRM
To compensate for process variation during circuit design the PV-aware circuit
models need to be used in new methods for circuit design and future design
tools and flows
D3.2.1 ST-I, UNBO, UNCA, UNRM: Circuit techniques, and speed-up
algorithms for PV-aware circuit simulation
Highlights:
–
–
–
Adaptive Body Bias technique has been implemented
First results of an optimization procedure for circuit design
Influence of random process variations on speed and energy consumption has been
analyzed
Change of focus: circuit design techniques rather than simulation
speed-up techniques
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 31
T3.2 UNBO: Adaptive Body Bias techniques
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 32
T3.2 UNCA: Influence of random process variations
on speed and energy consumption
clk
2W
D
W
clk
clk
clk
clk
*
*
2W
2W
W
4W
2W
D
Q
clk
W
W
4W
clk
*
*
4W
2W
(b)
2W
3W
0.24
3W
2W
*
D
Q
3W
(c)
*
*
clk
0.24
2W
clk
3W
(d)
*
*
*
*
Q
2W
*
Q
0.24
3W
D
clk
0.24
clk
2W
3W
3W 0.24
0.24
0.12
0.12
1,4
*
*
0.24
3W
3W
0.12 0.12 0.12
*
*
3W
3W
Qb
*
0.24
0.24
3W
2W
2W
2W
Db
3W
3W
clk
0.24 0.24 0.24
Q
2W
2W
0.24 2W
D
*
*
4W
clk
2W
clk
(a)
clk
clk
2W
(e)
Normalized Mean EDP ()
*
*
clk
clk
*
*
clk
clk
*
*
*
*
clk
HLFF
2
MC MOS
SAFF
SDFF
TGMS
1,3
1,2
1,1
1,0
(a)
0,9
0,8
0,7
0,6
0,5
0,12
Flip-Flops circuits: (a) TGMS; (b) MC2MOS; (c) SAFF; (d) HLFF; (e) SDFF
0,18
0,24
0,30
0,36
0,42
0,48
0,54
0,60
0,66
0,72
Normalized EDP Std. Dev. (
W (m)
HLFF
1,0
2
MC MOS
SAFF
SDFF
TGMS
0,8
(b)
0,6
0,4
0,12
0,18
0,24
0,30
0,36
0,42
0,48
0,54
0,60
0,66
0,72
W (m)
EDP Variability (3[%]
30
HLFF
2
MC MOS
SAFF
SDFF
TGMS
25
20
(c)
15
10
5
0
0,12
0,18
0,24
0,30
0,36
0,42
0,48
W (m)
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 33
0,54
0,60
0,66
0,72
T3.2 UNRM STI: optimization procedure for circuit
design
First results on on optimization procedure obtained
Performance index can be reduced to 0.021 of first attempt
Learning machines defined:
– Artificial Neural Networks
– Support Vector Machines
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 34
WP3: Progress, high- and lowlights
Task T3.3: PV-aware design
Partners (underlined task leader): POLI, CSEM, IFXA, LETI, NXP, UPC
Solutions for PV-aware circuit design are proposed by either a monitor & control
strategy or by development of low PV sensitive standard cell libraries.
Inherently variability robust designs are introduced by restricted design rules,
redundant/spare transistors and self-timed logic.
D3.3.1 CSEM, IFXA, LETI, NXP, POLI, UPC: PV-tolerant schematics evaluation
and Monitor & Control (M&C) strategies in digital and AMS&RF
Highlights:
–
–
–
–
–
–
new methodologies for the assessment of reliability, including PV and aging
monitor and control strategies on AMS&RF circuits
M&C strategies proposing new PVT monitors
automated monitor insertion methodology
sleep transistors used for power-gating
design strategies for PV tolerant circuits
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 35
T3.3 IFX: monitor & control strategies on AMS&RF
control
voltage
...
Inv 1
...
Inv 2
...
Inv n
switch on-voltage
ref.
Phase
Frequency
Detector
Charge
Pump
Loop
Filter
Ringo
Monitor
MODERN 1st Year Review
June 22, 2010
Frequency
Divider
CONFIDENTIAL 36
T3.3 LETI: PV aware solutions for digital
QN
C
In_A
T1
RN
T3
T2
D
B
Latch
T4
CP
T5
Select
T6
Transition detector
In_A
CLK_LEAF
Sensor
QN : Warning / Error
D
Datapath
Q
CLK_DFF
Delay D1
RN : Reset
(a)
n2
Delay D2
n1
n3
Delay D3
CP
Pulse generator
DFF
CLK_LEAF
Clock
Tree
Time window
generator (CC)
W1 ratio
CLK_LEAF
CLK_DFF
W2 ratio
Temp/Power
0,9
1
1,1
1,2
0,9
1
1,1
1,2
-40
D2
103,29
102,40
99,61
98,70
91,90
91,27
90,92
90,70
98,87
96,01
94,16
93,35
90,17
89,48
89,35
89,11
92,34
89,62
88,61
89,06
88,10
87,92
87,79
93,11
91,61
90,33
88,65
87,63
87,38
87,24
CP
25
80
(b)
125
n1
n2
95,12
n3
D2
95,45
D3
CP
MODERN 1st Year Review
June 22, 2010
CLK_DFF
D2
CONFIDENTIAL 37
Detection
window
T3.3 POLI: PV effects in Power-Managed Circuits
MODERN 1st Year Review
June 22, 2010
bench
fnom
fwc
ftuned
b1
1.00
0.74
1.01
b2
1.00
0.74
1.04
b3
1.00
0.79
1.02
b4
1.00
0.76
1.03
b5
1.00
0.76
1.02
b6
1.00
0.74
1.01
b7
1.00
0.77
1.05
b8
1.00
0.55
1.03
Δ
0%
-27%
+2%
CONFIDENTIAL 38
T3.3 CSEM&UPC: PV tolerant circuits
The work done by CSEM :
– Source biasing
– Standard Cell Library using a few cells to provide a better compensation of
PV effects
– Standard Cell Library using regular layout or restricted design rules, with or
without redundancy
– Probabilistic CMOS (PCMOS) taking into account that each gate has a
probability of failure.
– Approximate arithmetic
The work of UPC has involved the following topics:
– Regular configurable cell (VCTA) design
– Probabilistic evaluation of digital circuits
– Approach to digital logic tolerant to noise
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 39
WP3: Progress, high- and lowlights
Task T3.4: Design for low noise and EMI/EMC
Partners: NXP, LIRM, ST-I
Next to process variation there is also a large contribution to the timing variation from
EMI/EMC related issues. Additionally, due to miniaturisation and co-habitation of
AMS&RF the analogue circuits risks suffering from the digital noise. New design
techniques will be proposed to suppress and canalise noise and EMI for improved
reliability of the complete electrical system.
D3.4.1 LIRM, ST-IM: Impact of supply noise, and clock distribution on EMI and circuit timing
D3.4.2 NXP: RF-interaction models for combined PCB-package-IC
Highlights
–
–
–
–
–
Significant attenuation in EM conducted emissions by decoupling insertion & optimization
Successful tape-out following methodology
flow allowing simulating the time domain evolutions of the magnetic emissions
validated by comparing the predicted emissions of two ICs
RF interaction models improved by: Parasitic extraction, De-embedding techniques, package
modelling
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 40
T3.4 STI&LIRM: magnetic field simulation flow
Measurement
MODERN 1st Year Review
June 22, 2010
Simulation
CONFIDENTIAL 41
T3.4 NXP: RF interaction models PCB-package-IC
Overview de-embedding methods
Reference simulation design flow
Vehicle: characterization board BGU7003
Specs
Initial circuit
design
(Cadence)
Simulation
Specs
Package/PCB
3D-modeling
(HFSS)
Refe
De-embedding
in HFSS
Circuit
design
RC
extraction
Package
(HFSS)
renc
e flo
w
Simulation data
(‘HFSS’ de-embedding)
Char. board
behavior (HFSS)
Circuit design
Simulation
Chip layout
Measurement
raw data
Circuit simulation
of full design
(Cadence)
Measurement data
(‘meas’ de-embedding)
Measurement
de-embedding
method
Simulation data
open/short/empty
Simulation
raw data
Circuit
design
RC
extraction
Package
(HFSS)
d
are
mp
Co
Behavior
S-parameter
model
MSA
d
are
mp
Co
RC extraction
(Assura RF)
Measurement data
open/short/empty
Measurement
De-embedding
strategy in HFSS
d
are
mp
Co
Package and PCB model
Top level
chip layout
Simulation data
(‘meas’ de-embedding)
Measurement
de-embedding
method
Char. board
behavior (HFSS)
Circuit design including physical effects
Impact de-embedding methods: S11
Current mismatch: S11
S11
measurement raw
simulation raw
Delta S11
Delta S11
0.2
0.2
0.18
0.16
Delta (vector) nom
Delta (vector) nom
0.18
0.14
0.12
0.1
0.08
0.06
0.04
0.16
0.14
0.12
0.1
0.08
0.06
0.04
0.02
0.02
Measurement low
Simulation low
Measurement average
Simulation nominal
Measurement high
Simulation high
0
0.00E+00
1.00E+09
Delta RC nominal
2.00E+09
3.00E+09
Target
Measurement
current mismatch *
Simulation
target
4.00E+09
5.00E+09
0
0.00E+00
6.00E+09
Frequency (Hz)
* mismatch average measurement
and nominal simulation
MODERN 1st Year Review
June 22, 2010
1.00E+09
Sim (M-Meth RC) - Meas(M-Meth)
Target
simulation – HFSS meth, nominal (reference)
simulation – M-Meth, nominal
Measurement, average
CONFIDENTIAL 42
2.00E+09
3.00E+09
Sim(raw) - Meas(raw)
Sim(HFSS RC) - Meas(M-Meth)
4.00E+09
5.00E+09
6.00E+09
Frequency (Hz)
simulation – HFSS meth, nominal (reference)
simulation – M-Meth, nominal
simulation raw – meas. raw, nominal
target
WP3: Technical status and achievements of
deliverables (incl. changes)
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 43
WP3: Cooperation
WP leader: NXP
Collaborations
–
NXP, TUD, TUE
•
•
•
•
–
UNIRM UNBO STI TUD
•
•
•
–
Poli relies on Leti to receive tools for var. assessment
CSEM, UPC, LETI, LIRM
•
•
•
–
Regular email and material exchange
STI and UNRM face 2 face an almost weekly phone contact
UNBO has strong collaboration with STI
POLI, LETI
•
–
NXP delivers path delay measurement data,
TUE STA timing correlation
TUD delivers models at transistor level
Regular face-to-face meetings and conference calls
Discussions on tolerant circuits and regular layouts
LETI and LIRM have strong collaboration on M&C , regualr phone calls
UPC has contac with LETI and CSEM on temp. mon. and regular layouts
NXP LIRM ST
•
Conference calls
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 44
WP3: Dissemination (publications, patents), exploitation
Accepted:
–
–
–
–
–
–
–
–
–
Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs, "A Simplified Transistor Model for CMOS Timing Analysis", Proceedings of
ProRISC 2009
Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs, "RDE-Based Transistor-Level Gate Simulation for Statistical Static Timing
Analysis", Proceedings of DAC 2010.
Ashish Nigam, Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs, "Statistical Moment Estimation in Circuit Simulation",
Proceedings of VARI 2010
Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs, "Transistor Level Waveform Evaluation for Timing Analysis", Proceedings
of VARI 2010.
P. Joubert Doriol, C. Forzan, D. Villa, D. Pandini, R. Castellan, D. Cervini, M. Rotigni, G. Graziosi, G. Contarino, and E. Marzorati,
“Power Rail Noise Minimization for EMC-aware Design,” in Proc. SNUG, Mar. 2009.
P. Joubert Doriol, Y. Villavicencio, C. Forzan, M. Rotigni, G. Graziosi, and D. Pandini, “EMC-aware Design on a Microcontroller for
Automotive Applications,” in Proc. DATE, Apr. 2009.
G. Graziosi, P. Joubert Doriol, Y. Villavicencio, C. Forzan, M. Rotigni, and D. Pandini, “Advanced Modeling Techniques for Systemlevel Power Integrity and EMC Analysis,” in Proc. EMPC, Jun. 2009.
C. Forzan and D. Pandini, “Statistical Static Timing Analysis: A Survey,” Integration, the VLSI Journal, vol. 42, pp. 409-435, Jun. 2009.
P. Joubert Doriol, Y. Villavicencio, C. Forzan, M. Rotigni, G. Graziosi, and D. Pandini, “Electromagnetic Interference Reduction on an
Automotive Microcontroller,” in Proc. Design Automation Conf., Jul. 2009
Submitted:
–
–
–
–
Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs, "Transistor-Level Gate Modeling for Nano CMOS Circuit Verification
Considering Statistical Process Variations", submitted to PATMOS 2010
Amir Zjajo, Qin Tang, Michel Berkelaar, Nick van der Meijs, "Noise Analysis of Non-Linear Dynamic Integrated Circuits", submitted to
CICC 2010 pdf
Amir Zjajo, Qin Tang, Jose Pineda de Gyvez, Michel Berkelaar, Alessandro Di Bucchianico, Nick van der Meijs, "Stochastic Analysis of
Deep-Submicron CMOS Process for Reliable Circuits Designs", submitted to IEEE Transactions on Circuits and Systems-I: Regular
Papers.
Amir Zjajo, Manuel Barragan, Jose Pineda de Gyvez, "Process Variation Monitoring Enhanced Calibration and Debugging of Multi-Step
Analog to Digital Converters", submitted to IEEE Transactions on Circuits and Systems-I: Regular Papers.
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 45
WP3: Other issues, Q&A
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 46
WP4: Relationship between workpackages
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 47
WP4: Progress, high- and lowlights
Task T4.x: Task name
Partners (underlined task leader):
Explain in a few words: goal of task, what you did this period, what will be
delivered and when.
Explain in a few words: what went well, better than expected and what went worse
than expected; describe corrective actions.
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 48
WP4: Technical status and achievements of
deliverables (incl. changes)
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 49
WP4: Cooperation
WP leader: ST-I
If strong dependence on partners: list partners, describe dependence
Collaboration with partners: list partners, collaboration (division of labor, role, …)
Face to face meetings with: list partners (when)
Telephone conferences with: list partners (when)
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 50
WP4: Dissemination (publications, patents), exploitation
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 51
WP4: Other issues, Q&A
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 52
WP5: Relationship between workpackages
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 53
WP5: Progress, high- and lowlights
Task T5.x: Task name
Partners (underlined task leader):
Explain in a few words: goal of task, what you did this period, what will be
delivered and when.
Explain in a few words: what went well, better than expected and what went worse
than expected; describe corrective actions.
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 54
WP5: Technical status and achievements of
deliverables (incl. changes)
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 55
WP5: Cooperation
WP leader: NMX
If strong dependence on partners: list partners, describe dependence
Collaboration with partners: list partners, collaboration (division of labor, role, …)
Face to face meetings with: list partners (when)
Telephone conferences with: list partners (when)
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 56
WP5: Dissemination (publications, patents), exploitation
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 57
WP5: Other issues, Q&A
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 58
MODERN 1st Year Review
June 22, 2010
CONFIDENTIAL 59