Transcript MODERN presentation template

WP5 agenda
Deliverables (incl. changes)
Demonstrator goals w.r.t. related project tasks
Major achievements, highlights / lowlights and comparison w.r.t. state
of the art
Demo’s and technical highlights:
– Thales: Philippe Millet / Simon Heywood “License plate detection
implementation on FPGA of robust parallel computing architecture ”
– UNBO / STI: Davide Rossi “Design flow validation for via/metal
programmable gate arrays”
– Tiempo: Marc Renaudin
– UPC: Francesc Moll Echeto
– IFXA/IMCA: Michael Fulde
– LETI: Edith Beigne
– AMS: Alexander Steinmar
Q&A
MODERN Final Review
May 3rd, 2012
CONFIDENTIAL
1
DELIVERABLES
D5.1.3: TUGI, AMS, NMX, STF2
“PV statistical data analysis coming from standard and improved test
structures in different technologies”
D5.2.3: TMPO, UPC, NXP, IFXA, LETI,
“test chip characterization (evaluation to show effectiveness of PVT
circuitry, of basic processing circuits implemented with regular
layouts,), calibration of PV robust analysis flows”
In Amendment n. 10 TUGI activity has been carved out
D5.3.3: ST-I, THL, NXP
“Trial PDKs (by ST-I), application programming on robust parallel
architectures. Software prototype implementation of parameterized
design methodology and MOR for statistical parameter variations”
Milestone M5.2 ‘Demonstrator final results’ passed
MODERN Final Review
May 3rd, 2012
CONFIDENTIAL
2
Demonstrator goals w.r.t. related project tasks
Logic CMOS
Tech. nodes:
65, 40, 32nm
Performance
Robustness
Monitoring (T3.3)
Redundancy (T3.3)
Adaptation (T4.1)
Regularity (T4.4) HW & SW
Robust architectures (T4.5) HW & SW
RF / AMS
Tech. nodes:
65, 32, 28nm
Reliability
Aging
Noise
Monitor &
Control (T3.3)
CONFIDENTIAL
RESULTS T5.1
OWNER NODE CONTENT
(nm)
NMX
/ NVM Combined
Micron
mismatch test
structures
AMS
Power Kelvin RON
probe;
Matching
multiplexer
ST-F
Logic Kelvin
mismatch
measurements
Highlights /
Lowlights
+ Works fine
- Not tested yet on
aggressive CMOS
+ Functional
Major achievements
Poly dummy analysis
Improved accuracy and
repeatability;
+ Mismatch vs
Ok w.r.t. standard
spacing
structures,
- Gain measures not Accuracy for mean
clear
values
Comparison w.r.t.
state of the art
Decoupling among
poly CD and implant
overlap (*)
Applied to power
devices
Trade off: accuracy vs.
complex and long
e-test
(*) L. Bortesi, L. Vendrame, G. Fontana,
“Combined test structure for systematic and stochastic Mosfets and gate resistance process variation assessment”,
IEEE Conference on Microelectronics Test Structures, March 2010, pp 226-230
MODERN Final Review
May 3rd, 2012
CONFIDENTIAL
4
RESULTS T5.2 - 1
OWNER NODE CONTENT
Highlights /
Major achievements
(nm)
Lowlights
IFXA
32 M&C:
+ Works as intended Degradation measured
IMCA
OPA and VCO
1st time for 32nm analog
and RF building blocks
IFXA
IMCA
IFXA
IMCA
32
IFXA
IMCA
28
TMPO
32
32
Comparison w.r.t.
state of the art
Building blocks are
“state-of-the-art” but
aging new
characterization
methods introduced
M&C:
+ Works as intended Error correction for aging Nothing comparable
SAR-ADC
in ADC proven on silicon published for ADCs
M&C: burn in, + All structures and M&C methods proven on Nothing comparable
chopping, auto- modes functional;
silicon
published for
zeroing
- Autozeroing still in
analog/mixed-signal
Lab
DCDC
+ All structures and Digital DCDC in 28nm
1st DCDC in 28nm
converter and modes functional;
with good efficiency
matching
- no degradation due
to hard-failures
Variability
+ Design and
Robust, variabilityUnique CAD flow
Tolerant
fabrication of a fully tolerant clock-less delay- enabling the
Asynchronous delay insensitive
insensitive circuits and fabrication of standard
microcontroller digital sub-system
associated CAD flow
cell based delay
- fabrication delay
insensitive circuits
MODERN Final Review
May 3rd, 2012
CONFIDENTIAL
5
RESULTS T5.2 - 2
OWNER NODE CONTENT
(nm)
UPC
40
VCDL with
regular
structures
Major achievements
UPC
65
Highlights /
Lowlights
evaluation of
lithography-induced
variations using a
regular fabric
proposal (VCTA).
LNA with M&C Thermal monitoring
of RF figures of merit
like gain.
demonstrated,
Comparison w.r.t.
state of the art
Results confirm a
Impact of regularity on
measurable difference in PV has not been
the variability of regular conclusively measured
VCTA chains w.r.t. FC
before
Novel technique to
embed analogue / RF
circuits in feedback
loops using temperature
as observable
UPC
65
Adjustable
- results partially
VCO and ILFD differs from
simulations, due to a
bug in the EM
inductors modelling
(underestimation).
Operation principle and
the optimization tradeoffs involving power
consumption, tuning and
locking ranges of the
selected ILFD topology.
MODERN Final Review
May 3rd, 2012
Novel idea for noninvasive monitoring
and healing.
Comparison can only
be made with
electrically invasive
techniques.
The measurements did
not meet the expected
requirements.
CONFIDENTIAL
6
RESULTS T5.2 - 3
OWNER NODE CONTENT
(nm)
LETI
32
Adaptive
Voltage and
frequency
scaling finegrain processor
cluster
THALES FPGA Robust parallel
computing
architecture
Highlights /
Lowlights
Design of a fully
dynamically adaptive
architecture at finegrain using other WP
developments
Major achievements
+ multicore on FPGA
based on MicroBlaze
processors linked
with a NoC capable
of reconfiguring itself
after simulated
hardware failure of a
core.
- simpler application
than first targeted.
A license plate detection
application on a 16-core
architecture. 10 cores
are actually used, 1 is a
supervisor, 5 remain for
reconfiguration
purposes.
After hardware failure of
a core, the system
reconfigures itself and
starts again.
Full design and
verification flow for this
mixed-signal complex
SoC
MODERN Final Review
May 3rd, 2012
Comparison w.r.t.
state of the art
Compared to existing
techniques, fine-grain
is the solution to face
in-die process
variations.
Approach of
reconfiguring the
multicore after failure
by doing task
migration.
Several projects are in
this direction like
ADAM (French ANR),
Recomp (Artemis) or
Flextiles (FP7).
CONFIDENTIAL
7
RESULTS T5.2 - 4
OWNER NODE CONTENT
(nm)
NXP
65
production
based test chip
for substrate
noise modeling
verification:
Test chip B
(CLN65
design)
Major achievements
NXP
Substrate noise sensor
implemented in
production design
140
Highlights /
Lowlights
-Measurements
didn’t show the
expected
improvement in
digital noise
interference, while
using “clean” well
biasing connections.
The root-cause is
being investigated
production
- the first silicon
based test chip results cannot
for substrate
provide any insights
noise modeling into the circuit
verification:
behaviour.
(CMOS14)
Comparison w.r.t.
state of the art
Various substrate
isolation methodologies
implemented on
production design
MODERN Final Review
May 3rd, 2012
CONFIDENTIAL
8
RESULTS T5.3
OWNER
NODE CONTENT
(nm)
THALES
-
ST-I
-
ST-I
-
NXP
-
SNPS
-
Highlights /
Major achievements
Lowlights
SW
Designed at SystemC Works fine on the FPGA
implementation of simulator level
implementation
the “licence plate
detection”
Trial PDK
+ The SVM method
Tool Model Builder based
used to replace the
on SVM works and is fully
RSM works fine
integrated in ST.
+ Models available
Simpler and more linear
and comparable to
industrial design flow.
those generated with
old methodology,
SOC design flow functional
Verification successful
of via/metal
programmable
gate array
Model Order
MORE used by
Increased automation and
Reduction and
partners (NMX/Micron) usability
parametrized
design
Various
+Implementation of
Results quality verified on
implementation
statistical IFM method same templates with
(based on IFM
different tools and methods
and direct
(see T2.2)
statistical method
MODERN Final Review
May 3rd, 2012
Comparison w.r.t. state
of the art
See note in T5.2
More efficient (time and
costs) than the previous
RSM (see project
MANON FP7-PEOPLEMCA-IAPP- 251380)
Fabric usability
Steps toward analogue
synthesis
Enhancement of tool
capabilities,
performance and
usability
CONFIDENTIAL
9
…in summary
11 test chips
– 9 Silicon available (6 confirm the expectations, 3 require additional
investigations)
– 2 waiting for results
1 FPGA successful implementation
– HW &SW fully functional
– Practical example of a final application
3 SW / flows prototypes and a commercial SW enhancement
test structures revised and further improved with a trade-off among test
time / accuracy / complexity / silicon area
MODERN Final Review
May 3rd, 2012
CONFIDENTIAL 10
WP5 Demos and Technical highlights
Demo’s and technical highlights:
– Thales: Philippe Millet / Simon Heywood “License plate detection
implementation on FPGA of robust parallel computing architecture ”
– UNBO / STI: Davide Rossi “Design flow validation for via/metal
programmable gate arrays”
– Tiempo: Marc Renaudin
– UPC: Francesc Moll Echeto
– IFXA/IMCA Michael Fulde
– LETI: Edith Beigne
– AMS: Alexander Steinmar
MODERN 2010 Review
March 1st, 2011
CONFIDENTIAL 11
THALES - DEMO
MODERN Final Review
May 3rd, 2012
CONFIDENTIAL 12
Thales – DEMO
FPGA implementation of vehicle registration plate detection
application on robust parallel computing architecture
Mathematical
Morphology
Binarise
Input
Combine & filter
Apply mask
Algorithm locates and extracts vehicle
registration plate from a larger image
MODERN Final Review
May 3rd, 2012
CONFIDENTIAL 13
Multicore
architecture
8-bit DIP
switches
Virtex-6 FPGA
Console
& debug
DDR memory
Homogeneous
16-node design
Console
& debug
FPGA
0
Thales NoC
1
4
5
Node
DDR
memory
Router
Node architecture
Microblaze
processor
Memory
(BRAM)
2
3
6
7
8
9
12
13
10
11
14
15
AXI bus
Network
interface
MODERN Final Review
May 3rd, 2012
CONFIDENTIAL 14
On-chip
network
Boot process
Supervisor node starts
first & initialises
hardware
Initialisation code
Console
& debug
FPGA
0
1
4
5
2
3
6
7
8
9
12
13
10
11
14
15
DDR
memory
MODERN Final Review
May 3rd, 2012
CONFIDENTIAL 15
Boot process
Application binaries read
from DDR memory &
sent to allocated nodes
Boot images sent to
processing nodes
Console
& debug
FPGA
0
1
4
5
2
3
6
7
8
9
12
13
10
11
14
15
DDR
memory
MODERN Final Review
May 3rd, 2012
CONFIDENTIAL 16
Console output – no faults
Thales vehicle registration plate detection
[ 0] hal_supervisor.c: Booting tile 1
[ 0] hal_supervisor.c: Booting tile 2
[ 0] hal_supervisor.c: Booting tile 5
[ 0] hal_supervisor.c: Booting tile 6
[ 0] hal_supervisor.c: Booting tile 7
[ 0] hal_supervisor.c: Booting tile 8
[ 0] hal_supervisor.c: Booting tile 9
[ 0] hal_supervisor.c: Booting tile 12
[ 0] hal_supervisor.c: Booting tile 13
...
[ 0] hal_msg.c: Raw packet sent (node=8, type=0, chan=0, r=0, size=19200)
[ 8] hal_msg.c: Raw packet received (type=0, chan=0, r=0, size=19200)
[ 8] hal_msg.c: Raw packet sent (node=0, type=0, chan=0, r=0, size=19200)
[ 0] hal_msg.c: Raw packet received (type=0, chan=0, r=0, size=19200)
[ 0] hal_msg.c: Raw packet sent (node=9, type=0, chan=0, r=0, size=19200)
[ 9] hal_msg.c: Raw packet received (type=0, chan=0, r=0, size=19200)
[ 9] hal_msg.c: Raw packet sent (node=0, type=0, chan=0, r=0, size=19200)
[ 0] hal_msg.c: Raw packet received (type=0, chan=0, r=0, size=19200)
[ 0] hal_msg.c: Raw packet sent (node=12, type=0, chan=0, r=0, size=19200)
[12] hal_msg.c: Raw packet received (type=0, chan=0, r=0, size=19200)
[12] hal_msg.c: Raw packet sent (node=0, type=0, chan=0, r=0, size=19200)
[ 0] hal_msg.c: Raw packet received (type=0, chan=0, r=0, size=19200)
[ 0] hal_msg.c: Raw packet sent (node=13, type=0, chan=0, r=0, size=19200)
[13] hal_msg.c: Raw packet received (type=0, chan=0, r=0, size=19200)
[13] hal_msg.c: Raw packet sent (node=0, type=0, chan=0, r=0, size=19200)
[ 0] hal_msg.c: Raw packet received (type=0, chan=0, r=0, size=19200)
[ 0] hal_msg.c: Raw packet sent (node=1, type=0, chan=0, r=0, size=19200)
[ 0] hal_msg.c: Raw packet sent (node=1, type=0, chan=0, r=0, size=19200)
[ 1] hal_msg.c: Raw packet received (type=0, chan=0, r=0, size=19200)
...
MODERN Final Review
May 3rd, 2012
Supervisor starts
Application binaries sent to
allocated processing nodes
NoC messages carrying
application data
CONFIDENTIAL 17
Boot process – reconfiguration
Supervisor detects
a faulty node
Reconfiguration
manager
Console
& debug
Chip restarts
Reconfiguration
manager
reallocates task to
a spare node
FPGA
0
1
4
5
2
3
6
7
8
9
12
13
10
11
14
15
DDR
memory
MODERN Final Review
May 3rd, 2012
CONFIDENTIAL 18
Faulty node
Task reallocated
to node 15
Console output – node 5 faulty
Thales vehicle registration plate detection
[ 0] hal_supervisor.c: Tile 5 marked as faulty
[ 0] hal_supervisor.c: Using tile 15 as substitute
[ 0] hal_supervisor.c: Booting tile 1
[ 0] hal_msg.c: Tile message sent (node=1, type=11, chan=0, r=0, size=8)
[ 1] hal_msg.c: Remapped tile 15 as tile 5
[ 0] hal_supervisor.c: Booting tile 2
[ 0] hal_msg.c: Tile message sent (node=2, type=11, chan=0, r=0, size=8)
[ 2] hal_msg.c: Remapped tile 15 as tile 5
[ 0] hal_supervisor.c: Booting tile 5
[ 0] hal_msg.c: Tile message sent (node=5, type=11, chan=0, r=0, size=8)
[ 5] hal_msg.c: Remapped tile 15 as tile 5
[ 0] hal_supervisor.c: Booting tile 6
[ 0] hal_msg.c: Tile message sent (node=6, type=11, chan=0, r=0, size=8)
[ 6] hal_msg.c: Remapped tile 15 as tile 5
[ 0] hal_supervisor.c: Booting tile 7
[ 0] hal_msg.c: Tile message sent (node=7, type=11, chan=0, r=0, size=8)
[ 7] hal_msg.c: Remapped tile 15 as tile 5
[ 0] hal_supervisor.c: Booting tile 8
[ 0] hal_msg.c: Tile message sent (node=8, type=11, chan=0, r=0, size=8)
[ 8] hal_msg.c: Remapped tile 15 as tile 5
[ 0] hal_supervisor.c: Booting tile 9
[ 0] hal_msg.c: Tile message sent (node=9, type=11, chan=0, r=0, size=8)
[ 9] hal_msg.c: Remapped tile 15 as tile 5
[ 0] hal_supervisor.c: Booting tile 12
[ 0] hal_msg.c: Tile message sent (node=12, type=11, chan=0, r=0, size=8)
[12] hal_msg.c: Remapped tile 15 as tile 5
[ 0] hal_supervisor.c: Booting tile 13
[ 0] hal_msg.c: Tile message sent (node=13, type=11, chan=0, r=0, size=8)
[13] hal_msg.c: Remapped tile 15 as tile 5
...
[ 0] hal_msg.c: Raw packet sent (node=8, type=0, chan=0, r=0, size=19200)
[ 8] hal_msg.c: Raw packet received (type=0, chan=0, r=0, size=19200)
[ 8] hal_msg.c: Raw packet sent (node=0, type=0, chan=0, r=0, size=19200)
[ 0] hal_msg.c: Raw packet received (type=0, chan=0, r=0, size=19200)
...
MODERN Final Review
May 3rd, 2012
Supervisor starts
Faulty tile replaced by spare
Other nodes are notified of
the reconfiguration as they
are booted
NoC messages carrying
application data
CONFIDENTIAL 19
UNBO ST- I - DEMO
MODERN Final Review
May 3rd, 2012
CONFIDENTIAL 20
Design flow validation for metal
programmable gate array
Griffy-C Code
Signoff,
packaging
Grammar
Check
Synthesis and
P&R
DFG
Check
VHDL code
generation
Routing-only
Detection
Griffy Netlist
Generation
ILP
Extraction
Emulation
Model
Pipeline
Management
DFG Graph
Dump
VIDEO: Griffy-C code compilation, VHDL
code generation, implementation flow
VIDEO: layout view of a customized
metal programmable gate array
CONFIDENTIAL
Design flow validation for via programmable
gate array
VIDEO: Griffy-C code compilation,
placement and routing
VIDEO: MT-PiCoGA
customization flow
CONFIDENTIAL
MT-DREAM SoC
Focus on:
• 3.5x3.5 = 12,25 mm2 cmos065LP
• 200 MHz wccom target freq.
• Separate power domains 2 macro
Macro Instances:
• MT-PiCoG4 macro
• PiCoGA elab. flow structure
mapped on FourTunE cells
(metal programmable)
Customization:1
• Context 0 → ycc2rgb conversion
• Context 1 → test patterns
• Context 2 → ycc2rgb conversion
CRC Ethernet
• Context 3
FFT 1920
CONFIDENTIAL
IFXA/IMCA
MODERN Final Review
May 3rd, 2012
CONFIDENTIAL 24
IFXA/IMCA: Aging Characterization and Compensation of
AMS/RF Building Blocks in 32nm CMOS
OpAmp
VCO
compensation of
aging induced offset
model-hardware correlation aging simulation
fast transient effects characterized
MODERN Final Review
May 3rd, 2012
CONFIDENTIAL 25
IFXA/IMCA: 12bit ADC with error correction
12-bit SAR-ADC implemented in 32nm CMOS (planar HKMG)
Programmable SAR algorithm: non-binary & binary
Typical performance at VDD=1V
– fsample=5MS/s, fsignal 1.5MHz
– IDD=10mA (80% buffer)
– ENOB > 10Bit
Diff. Cap.-Net.
Comparator
SAR-Logic
- Counter
- Alu
- switchable ROM
190um x 138um = 0.026mm2
Buffer
Digital Output
Vrefp AIN Vrefn
MODERN Final Review
May 3rd, 2012
CONFIDENTIAL 26
IFXA/IMCA: 12bit ADC with error correction
Degradation of ENOBs at high fsample due to input buffer
– Non-binary search enables error correction and higher sample rate
Error correction works also at low sample rates !!!
– Non-binary at t0  leakage currents (gate leakage, GIDL, …)
– Binary at t0  hysteresis, transient mismatch & leakage currents
– Aged: Non-binary search compensates for aging effects
MODERN Final Review
May 3rd, 2012
CONFIDENTIAL 27
IFXA/IMCA: Digital DCDC in 28nm
10µF
DPWM
1.6MHz
MP
PFM
mode
DEMOS
MN
Clk 208MHz
3.3µH
22µF
current &
voltage sense
computational unit
+
z-1
z-1
5
D
A
z-1
Figure 6: Measurement result
Coefficients A B C
Figure 1: Overall Architecture
1st integrated digital controlled DCDC in 28nm CMOS
Dedicated circuit concepts to deal with reliability in 28nm
Promising area scaling and power efficiency achieved
Accelerated aging tests prevented by hard-failures due to PCB limitations
MODERN Final Review
May 3rd, 2012
CONFIDENTIAL 28
UPC
MODERN Final Review
May 3rd, 2012
CONFIDENTIAL 29
UPC
Measurement results for 3 chips
– VCO+ILFD with digitally tunable range (65nm)
• Not conclusive due to mistake in L calculation
– Thermal sensor with LNA as CUT (65nm)
• New self calibrated thermal sensor
• Demonstration of link between performance and Temperature
– Regular vs Full Custom VCDL for PV characterization (40nm)
• Application of VCTA regular fabric
• Demonstrated smaller PV in regular circuits
• Observation of WID and D2D variations
MODERN Final Review
May 3rd, 2012
CONFIDENTIAL 30
UPC-Thermal sensor
Thermal sensor with compensation loop against variations in bias
MODERN Final Review
May 3rd, 2012
CONFIDENTIAL 31
UPC – LNA thermal sensing
Demonstrated correlation between sensor output and electrical
characteristics
MODERN Final Review
May 3rd, 2012
CONFIDENTIAL 32
UPC-Regular layout
Initial design had independent power voltage for delay chain and MUX
Final chip has tied voltages for delay chain and MUXs
Results show that delay chain is the dominant delay in the
measurements
Measured jitter demonstrates impact of regular layout
MODERN Final Review
May 3rd, 2012
CONFIDENTIAL 33
UPC- Regular layout results
MODERN Final Review
May 3rd, 2012
CONFIDENTIAL 34
AMS
MODERN Final Review
May 3rd, 2012
CONFIDENTIAL 35
AMS technical highlights Ia
Novel approach for HV MOS DC monitoring structures
–
–
–
–
Improved standard Kelvin Structures capable for process monitoring
Standard scribe line can be used
New approach does not need additional area for the additional sense pads
Useable for standard devices & butted devices (VBS=0)
a) Standard application for sence /force
b) Butted configuration
c) Implementation: left new, right standard
MODERN Final Review
May 3rd, 2012
CONFIDENTIAL 36
AMS technical highlights Ib - Results
Structure is capable for indicating
–
–
–
–
–
systematically design errors
Contact difficulties
Generation of process statistics
Accuracy improvement
Significant improvement for
high current applications
Performance of sence/force technique vs.
non s/f technique over device size
relative to standard structure
Proven repeatability based on outlier criterion for
contact and design errors
MODERN Final Review
May 3rd, 2012
CONFIDENTIAL 37
AMS technical highlights II
On-Chip Multiplexer Mismatch Structures
–
–
–
–
Support of distance dependent matching
Capable for voltages up to 50V
Capable for currents up to 20mA
Provides gate & drain multiplexing
Multiplexer principle
Extracted vth & mobility matching
Short vs. far distance matching
MODERN Final Review
May 3rd, 2012
CONFIDENTIAL 38
LETI
MODERN Final Review
May 3rd, 2012
CONFIDENTIAL 39
CEA-LETI Demonstrator
A fine grain Local Dynamic Adaptive voltage and frequency saling
architecture
Decision Maker
Parameter Control
V/F
V/F
V/F
V/F
V/F
V/F
V/F
V/F
V/F
V/F
V/F
V/F
V/F
V/F
V/F
V/F
V/F
V/F
V/F
V/F
V/F
V/F
V/F
V/F
Diagnostic
S
K
S
GALS
K : Actuators
S : Sensors
Circuit
S
Action
K
S
K
Digital Block
1 Power/Frequency domain
1
Soutenance de thèse - 9 décembre 2009 - Bettina Rebaud
CONFIDENTIAL
Demonstrator Architecture
Asynchronous NoC
WP4
4 XP70 µP
Dedicated memory
blocks
L2RAM
HWS & Periph.
Shared Memory
256KBytes
Hardware Synchronizer
& Peripherals
DMA engine
NI
NI
NI
V/F Local actuators
CDMA
(out of MODERN project)
AXI
Bridge
Timing Fault
Detectors
PVT sensors
WP3
clk_ref
Local Controller VH
CVP : Clock- VM
Vraiability-PowerVL
Asynchronous NoC
NI
F
V
CVP Sel. Sel.
NI
F
V
CVP Sel. Sel.
NI
NI
PE
PE
PE
PE
Processing
Element
Processing
Element
Processing
Element
Processing
Element
Voltage/Frequency domain
Voltage/Frequency domain
CONFIDENTIAL
Power Domains main characteristics
Each domain is an independant power and frequency domain :
– a GALS scheme within the cluster
– domains are synchronous islands using programmable
clock generator
– Within each domain, the logic core is supplied by Vcore
voltage generated from external available voltages :
VHigh/VMedium/VLow)
– Dynamic variability monitoring using timing fault
detection and low area PVT probes
Local fine grain power and variability management can be
executed during IP computation and communication
independently from the others
CONFIDENTIAL
Power domain ‘power modes’ (from WP4.1)
Frequency
FH
Failure area
FM
Vdd Hopping
transition
Frequency
adaptation
FL
Operating point
0
OFF
VL
VM
VH
Voltage
CONFIDENTIAL
Demonstrator Layout
Area:
–
2784 µm x 1400 µm
Technology:
STMicroelectronics CMOS032LP
AXI Bridge
DMA
Engine
HWS & Periph
–
PE0 + AVFS
PE1 + AVFS
Shared
Memory
Asynchronous Network on Chip
PE2
PE3
CONFIDENTIAL
Results (from back-end extracted simulations)
 For an area overhead of ~10% we can obtain from 20% to 45%
energy gain depending on :
• Intrinsic variability
• Workload balancing
160,00
3
Energy per instruction (pJ/inst)
140,00
+24%
120,00
2
VH
1V
100,00
*
VM
*
1V
*
+29%
20,00
0,00
300
Ideal AVFS
DVFS + margin
VDD hopping
VDD hopping +margin
+90%
40,00
400
VL
500
600
7.5%
1: Voltage drop due to HS
2: Power dissipated in HS
3: Frequency margin 60ps
80,00
60,00
1
700
800
900
1000
Frequency (MHz)
CONFIDENTIAL
TIEMPO
MODERN Final Review
May 3rd, 2012
CONFIDENTIAL 46
TIEMPO Work
Demonstrate variability-tolerant circuit design
– Delay insensitivity = correct independently of actual delays
– Design flow
– Test-chip fabrication using STMicroelectronics 32 nm process
– Test-chip characterization
Collaboration with STMicroelectronics and Leti
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Test-chip
Fully asynchronous
Fully digital
GPIO
TAM16
µC
About 500 Kgates
Use of a small set of
asynchronous cells
(13 functions, 50 layouts)
compliant with the standard
cell library
Serial_In/Out
RS232
Decoder
RAM
ROM
TIEMPO Test-Chip
STMicroelectronics
32nm process
48 pin QFN package
Taped-out in July 2011
Packaged silicon expected beginning of May (delayed)
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Design flow applied
Cells design (coll. Leti)
SystemVerilog / SDC
Cells characterization
Standard
cells
Synthesis using ACC
Validation
ACC
synthesis
Asynch
cells
Place and Route (coll. STM)
Validation
Verilog
SDC /
SDF
SystemVerilog
Benches
P&R
No timing closure
Simulation
Only 2 constraints
-
Max cap
-
Max transition
Physical
verifications
Tape-Out
Focus on physical verifications
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2012 – Do not copy/forward without
prior written approval from TIEMPO
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Test-chip characterization
Test-board development
– Power supplies, Host interface, PIOs
Test programs
– Microcontroller BIST
– ROM check
– RAM read/write test
– RS232 test and echo mode
– Instruction loops
– Loader to execute specific test programs
All these test programs provide an output status on the PIOs
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Test-chip characterization
Chips should be back early May
About 30 packaged circuits, 10 per wafer (slow, typical, fast)
Test and characterize speed and power w.r.t
–
–
–
–
Process conditions
Locations on the wafer
Operating voltages
Test programs
Characterization
corner 3
Characterization
corner 2
Characterization
corner 1
Scheduled by mid-June 2012
Functionally-guaranteed test chips automatically
deliver process-related timing information at their
primary outputs
COPYRIGHT TIEMPO S.A.S – 2012 – Do not
copy/forward without prior written approval from
TIEMPO
CONFIDENTIAL
MODERN Final Review
May 3rd, 2012
CONFIDENTIAL 52
MODERN Final Review
May 3rd, 2012
CONFIDENTIAL 53