Transcript MODERN presentation template

Agenda
MODERN WP3 Meeting
November 9
Catania, Italy
Version: 0.2
WP3: Wilmar Heuvelman
T3.1 Michel Berkelaar
T3.3 Massimo Poncino
T3.2 Igor Loi
T3.4 Rick Janssen
Contents
Objectives for WP3 meeting
Timeline
Matrix
Application overview per task
Gantt chart
MODERN General Meetings
Catania, Nov. 9 & 10, 2010
CONFIDENTIAL 2
Objectives
Opportunity to exchange results between partners, discussions
Reply on the feedback of the reviewers
– Identify key achievements/deliverables
– Identify links between other WP’s/Task
– Identify links to demonstrators (WP5)
Time line and planning
– Deliverables & Milestones
– Organisation
Matrix (Afternoon)
Gantt Chart (afternoon)
Summary for WP3 presentation in General meeting (10/11)
MODERN General Meetings
Catania, Nov. 9 & 10, 2010
CONFIDENTIAL 3
Timeline(1)
Review & Deliverables
Next review: March 1 2011-> deliverables 2010!
4th half year progress report-> end Feb 2011
Deliverables (all M24, end Feb 2011):
Number
D3.1.2
D3.2.2
Contributors
LIRM, NXP, ST-I, TUD, TUE, UNRM
NMX, NXP, UNBO, UNCA, UNGL, UNRM
Deliverable
Month
Statistical methodology for characterisation of digital and AMS&RF circuits
M24
Standardized PV-aware tools for simulation of digital blocks, AMS&RF blocks, and NVM arrays M24
D3.3.2
D3.4.3
CSEM, IFXA, LETI, NXP, POLI, UPC
NXP, ST-I
D3.4.4
ST-I
PV-tolerant lib cell designs and M&C implementation in digital and AMS&RF
Substrate RF coupling, RF co-simulator, Power Distribution Model (PDN) evaluation and
analysis flow for combined IC-package-PCB
Implementation and evaluation of clock tree synthesis techniques for low EMI
MODERN General Meetings
Catania, Nov. 9 & 10, 2010
CONFIDENTIAL 4
M24
M24
M24
Timeline(2)
Milestones
MODERN General Meetings
Catania, Nov. 9 & 10, 2010
CONFIDENTIAL 5
Matrix
Application overview per task and partner
Tasks
Circuit Models
Methods
Tools&Flows
PV aware
Circuits
EMI/EMC
Application
3.1
3.2
3.3
3.4
Digital
NXP,STI,TUD,TUE,
UNRM,LIRM
UNBO,NXP,STI,
UNCA,
UNGL,UNRM
POLI,LETI,UPC
STI,LIRM
AMS
STI,UNRM
NMX,STI,UNRM
IFX,UPC
NXP,STI
RF
NXP,STI
IFX
NXP
NVM
NMX
MODERN General Meetings
Catania, Nov. 9 & 10, 2010
CONFIDENTIAL 6
T3.1 Application overview
Tasks
Circuit
Models
Alternative to SSTA: RDE based TL
gate simulation (TUD)
Application
3.1
Cell level HDL models(UNRM,ST)
SSTA based on moment propagation
Digital
NXP,STI,TUD,
TUE,UNRM,LI
RM
AMS
STI,UNRM,NX
P
RF
NXP,STI
Surrogate behavourial
models(UNRM,ST)
Model Order Reduction (MOR)
NVM
MODERN General Meetings
Catania, Nov. 9 & 10, 2010
CONFIDENTIAL 7





First European Workshop on CMOS Variability
Need to meet industry and academia
Organized by LIRMM (Nadine Azemard)
Help of University of Glasgow, UK
Help of CEA-Leti, STMicroelectronics (Grenoble, Fr)
7
 50 participants
 Different countries
6
5
4
3
2
1
0
 Selected papers included in a special issue of The
Journal of Low Power Electronics (JOLPE).
CONFIDENTIAL
9
T3.2 Application overview
ABB & algorithms for FBB allocation
(UNBO)
Tasks
Methods
Tools&Flows
Application
3.2
Influence of PV on speed and energy
on logic (UNCA)
Digital
UNBO,NXP,STI, UNCA,
UNGL,UNRM
Circuit design optimization
(UNRM,STI)
Activity analysis tool(NXP)
AMS
NMX,STI,UNRM
Spice like simulation on sensing
memory circuit (NMX,UNGL)
RF
NVM
NMX
Upgrade on statistical circuit
simulator (UNGL)
MODERN General Meetings
Catania, Nov. 9 & 10, 2010
CONFIDENTIAL 10
T3.3 Application obverview
Tasks
Application
PV aware Circuits
Variablity assesment (IFX)
3.3
M&C for digital (POLI,LETI,UPC,STI)
and analog(IFX,UPC)
Tolerant redundant logic (UPC)
Digital
POLI,LETI,UPC
Modular power gating (POLI)
Regular cells (UPC)
AMS
IFX,UPC
RF
IFX
NVM
MODERN General Meetings
Catania, Nov. 9 & 10, 2010
CONFIDENTIAL 11
Task T3.3: Partner Participation in
subtasks
AMS &
Digital
RF
3.3.1 Variability Assessment
3.3.2 M&C Strategies
3.3.3 PV-aware Circuit-level
design
IFAT
IFAT
UPC
Delivs
D3.3.2
POLI
UPC
LETI
ST
UPC
ST?
CONFIDENTIAL
D3.3.2
D3.3.2
D3.3.3
T3.3
Partner Interaction and exchange
(Partner in a row might need from partners in a column)
POLI
IFAT
UPC
POLI
IFAT
UPC
CEA
ST
-
-
New Cell
Libraries
PV
Monitors
Tech
libraries
-
-
-
-
PV
monitors
(for WP4)
Tech
libraries
PV
monitors
-
Tech
libraries
-
-
Sleep cell
CEA
ST
Exchange
info on PV
monitors?
Exchange
info on PV
monitors
-
-
CONFIDENTIAL
T3.4 Application overview
Tasks
EMI/EMC
Power distribution model for chippackage-PCB (STI)
Application
3.4
Clock tree synthesis for low EMI
(STI)
Digital
STI,LIRM
Substrate noise (NXP)
Mutual interaction for RF-power
devices (NXP)
AMS
NXP,STI
RF
NXP
NVM
MODERN General Meetings
Catania, Nov. 9 & 10, 2010
CONFIDENTIAL 14
Gantt chart
Technical Annex
MODERN General Meetings
Catania, Nov. 9 & 10, 2010
CONFIDENTIAL 15
Gantt chart (proposed)
Mile-stone Show Gantt chart
Planned
for:
Highlight month: 21
KEY:Planned Duration
Planned % Finished
Actual Duration
Actual % Finished
################################################## 1/10 2/10 3/10 4/10 5/10 6/10 7/10 8/10 9/10 ############### 1/11 2/11 3/11 4/11 5/11 6/11 7/11 8/11 9/11 ############### 1/12 2/12
Planned Actual
Goals
3.1.1 NXP, ST-I1, TUD,
TUE, UNRM1,
Set of alternative symbolic models for lib cells
UNIRM2
3.1.2 LIRM, NXP, ST-I,
Statistical methodology for characterisation of
TUD, TUE, UNRM digital and AMS&RF circuits
3.1.3 NXP, STI, TUD, TUE, Automated and validated characterisation flow
UNRM
for lib cells, and AMS&RF blocks
3.2.1 ST-I1, UNBO, UNCA, Process development kit (PDK), circuit techniques,
UNRM1
and speed-up algorithms for PV-aware circuit
simulation
3.2.2 NMX, NXP, UNBO,
Standardized PV-aware tools for simulation of
UNCA, UNGL,
digital blocks, AMS&RF blocks, and NVM arrays
UNRM
3.2.3 NMX, UNBO, UNRM Integration and validation of high-speed PVaware simulation tools for digital blocks, AMS&RF
blocks, and NVM arrays
3.3.1 IFXA, LETI, POLI,
PV-tolerant schematics evaluation and Monitor &
UPC
Control (M&C) strategies in digital and AMS&RF
3.3.2 IFXA, LETI, POLI,
PV-tolerant lib cell designs and M&C
UPC
implementation in digital and AMS&RF
3.3.3 IFXA, UPC, POLI
Synthesis and simulation of digital blocks, and
measurement and verification of critical AMS&RF
3.4.1 LIRM, ST-I2
Impact of supply noise, and clock distribution on
EMI and circuit timing
3.4.2 NXP
RF-interaction models for combined PCBpackage-IC
3.4.3 NXP, ST-I
Substrate RF coupling, RF co-simulator, Power
Distribution Model (PDN) evaluation and analysis
flow for combined IC-package-PCB
3.4.4 ST-I
Implementation and evaluation of clock tree
synthesis techniques for low EMI
3.4.5 NXP
Design flow for RF co-habitation
3.4.6 NXP
Measurements of substrate noise monitor
3.4.7 ST-I
Design solutions for EMI-aware design for
automotive, and EMI evaluation of combined ICpackage-PCB
Dur
Star atio Star Dura
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%
Done
Prerequisit
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BLUE BLUE BLUE BLUE BLUE BLUE BLUE BLUE BLUE BLUE BLUE TRUE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE
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13 11 13
25 36
100%
-
M3.1
50%
D3.1.1
M3.2
0%
D3.1.2
-
100%
-
M3.3
13 11 13
50%
D3.2.1
M3.4
25 36
0%
D3.2.2
-
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BLUE BLUE BLUE BLUE BLUE BLUE TRUE TRUE TRUE TRUE TRUE TRUE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE
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TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
BLUE BLUE BLUE BLUE BLUE BLUE BLUE BLUE BLUE BLUE BLUE BLUE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE
1
1
11
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100%
M3.5
13 11 13
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50%
M3.6
25 36
0%
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1
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100%
1
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100%
13 11
13 11
25 11
50%
50%
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BLUE BLUE BLUE BLUE BLUE BLUE TRUE TRUE TRUE TRUE TRUE TRUE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE
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TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
BLUE BLUE BLUE BLUE BLUE BLUE BLUE BLUE BLUE BLUE BLUE BLUE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE
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BLUE BLUE BLUE BLUE BLUE BLUE TRUE TRUE TRUE TRUE TRUE TRUE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE
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TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
BLUE BLUE BLUE BLUE BLUE BLUE BLUE BLUE BLUE BLUE BLUE BLUE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE
M3.7
D3.4.2;
D5.2.1
BLUE BLUE BLUE BLUE BLUE BLUE BLUE BLUE BLUE BLUE BLUE BLUE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE
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BLUE BLUE BLUE BLUE BLUE BLUE TRUE TRUE TRUE TRUE TRUE TRUE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE
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BLUE BLUE BLUE BLUE BLUE BLUE TRUE TRUE TRUE TRUE TRUE TRUE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE
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TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
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TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
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TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
M3.8
M3.9
-
25 11
D3.4.1
D3.4.3
D3.4.3;
D5.2.2
25 11
D3.4.4
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MODERN General Meetings
Catania, Nov. 9 & 10, 2010
CONFIDENTIAL 16
Links to WP’s /Tasks
T3.1 Model Order Reduction(NXP) to T5.3(input)
T3.1 & T3.2(input) Trial PDK (STI,UNRM) to 5.3
T3.1 to WP2 (input)?
T3.2 to T5.1(input) and T2.3(input): char data used for checks(NMX)
– Input not necissarily but would be beneficial
T3.3 AMS M&C to T5.2(input) (IFX)
– Test structrures
– M&C
T3.3(input) fault detectors (LETI) T5.2
T3.4 to T5.2(input): substrate noise (NXP)
T3.4 to T3.1(input): MOR (NXP)
T3.4(input M12) to T4.2(input M24): low EMI arch (STI)
MODERN General Meetings
Catania, Nov. 9 & 10, 2010
CONFIDENTIAL 17
MODERN General Meetings
Catania, Nov. 9 & 10, 2010
CONFIDENTIAL 18