Transcript Introduction to VLSI Design

Sequential Circuits
IEP on Synthesis of Digital Design 2007
Sequential Circuits
S. Sundar Kumar Iyer
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IEP on Synthesis of Digital Design 2007
Sequential Circuits
Acknowledgement

Slides taken from
http://bwrc.eecs.berkeley.edu/IcBook/index.htm
which is the web-site of “Digital Integrated Circuit – A Design
Perspective” by Rabaey, Chandrakasan, Nicolic
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IEP on Synthesis of Digital Design 2007
Sequential Circuits
Outline
 Background
and naming conventions
 Timing constraints and stability issues
 MUX based latch and registers
 Cross-coupled pair
 Implementations
 Pseudo-static, C2MOS, TSPC, …
 Pipelining
 Schmitt
Trigger and Multivibrators
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Sequential Circuits
IEP on Synthesis of Digital Design 2007
Sequential Logic
Inputs
Outputs
COMBINATIONAL
LOGIC
Current State
Registers
Q
Next state
D
CLK
2 storage mechanisms
• positive feedback
• charge-based
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Sequential Circuits
IEP on Synthesis of Digital Design 2007
Naming Conventions
 Rabaey’s
Convention
 a latch is level sensitive
 a register is edge-triggered
 There
are many different naming
conventions
 For instance, many books call edgetriggered elements flip-flops
 This leads to confusion however
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Sequential Circuits
IEP on Synthesis of Digital Design 2007
Latch versus Register

Latch
stores data when
clock is low

Register
stores data when
clock rises
D Q
D Q
Clk
Clk
Clk
Clk
D
D
Q
Q
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IEP on Synthesis of Digital Design 2007
Sequential Circuits
Latches
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Sequential Circuits
IEP on Synthesis of Digital Design 2007
Latch-Based Design
• N latch is transparent
when f = 0
• P latch is transparent
when f = 1
f
N
Latch
Logic
P
Latch
Logic
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Sequential Circuits
IEP on Synthesis of Digital Design 2007
Timing Definitions
CLK
t
tsu
D
D
thold
DATA
STABLE
Q
CLK
t
tc 2
Q
Register
q
DATA
STABLE
t
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Sequential Circuits
IEP on Synthesis of Digital Design 2007
Characterizing Timing
tD 2
D
Q
Clk
tC 2
D
Q
Q
Clk
Q
Register
tC 2
Q
Latch
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Sequential Circuits
IEP on Synthesis of Digital Design 2007
Maximum Clock Frequency
FF’s
f
LOGIC
tp,comb
tclk-Q + tp,comb + tsetup = T
Also:
tcdreg + tcdlogic > thold
tcd: contamination delay
= minimum delay
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Sequential Circuits
IEP on Synthesis of Digital Design 2007
Positive Feedback: Bi-Stability
Vi2
V o1
1
o
V
1
o
V
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i
V
V i1
V o2
A
V i 2 = V o1
1
o
V
52
i
V
C
B
V i 1 = V o2
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IEP on Synthesis of Digital Design 2007
Sequential Circuits
Meta-Stability
Gain should be larger than 1 in the transition region
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Sequential Circuits
IEP on Synthesis of Digital Design 2007
Writing into a Static Latch
Use the clock as a decoupling signal,
that distinguishes between the transparent and opaque states
CLK
CLK
Q
CLK
D
D
CLK
D
CLK
Converting into a MUX
Forcing the state
(can implement as NMOS-only)
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Sequential Circuits
IEP on Synthesis of Digital Design 2007
Mux-Based Latches
Negative latch
Positive latch
(transparent when CLK= 0) (transparent when CLK= 1)
1
D
0
Q
0
CLK
Q  Clk  Q  Clk  In
D
Q
1
CLK
Q  Clk  Q  Clk  In
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Sequential Circuits
IEP on Synthesis of Digital Design 2007
Mux-Based Latch
CLK
Q
CLK
D
CLK
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Sequential Circuits
IEP on Synthesis of Digital Design 2007
Mux-Based Latch
CLK
QM
CLK
QM
CLK
CLK
NMOS only
Non-overlapping clocks
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IEP on Synthesis of Digital Design 2007
Master-Slave (Edge-Triggered)
Register
Sequential Circuits
Two opposite latches trigger on edge
Also called master-slave latch pair
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Sequential Circuits
IEP on Synthesis of Digital Design 2007
Master-Slave Register
Multiplexer-based latch pair
I2
D
T2
I3
I5
T4
I4
T3
I6
Q
QM
I1
T1
CLK
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Sequential Circuits
IEP on Synthesis of Digital Design 2007
Clk-Q Delay
2.5
Volts
CLK
1.5
0.5
2 0.5
0
D
tc 2
q(lh)
tc 2
q(hl)
Q
0.5
1
1.5
time, nsec
2
2.5
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IEP on Synthesis of Digital Design 2007
Sequential Circuits
Setup Time
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Sequential Circuits
IEP on Synthesis of Digital Design 2007
Reduced Clock Load
Master-Slave Register
CLK
D
T1
CLK
CLK
I1
I2
T2
CLK
I3
Q
I4
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Sequential Circuits
IEP on Synthesis of Digital Design 2007
Avoiding Clock Overlap
X
CLK
CLK
Q
D
A
B
CLK
CLK
(a) Schematic diagram
CLK
CLK
(b) Overlapping clock pairs
Need to use non-overlapping clocks f1 and f2
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Must be careful about limiting the non-overlapping period
Sequential Circuits
IEP on Synthesis of Digital Design 2007
Overpowering the Feedback Loop ─
Cross-Coupled Pairs
NOR-based set-reset
S
R
S
R
Q
Q
0
0
Q
Q
1
0
1
0
0
1
1
1
0
0
1
0
Q
Q
S
Q
R
Q
Forbidden State
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Sequential Circuits
IEP on Synthesis of Digital Design 2007
Cross-Coupled NAND
Added clock
Cross-coupled NANDs
S
VDD
M2
Q
M4
Q
Q
R
Q
CLK
M6
S
M5
M1
M3
M8
CLK
M7
R
This is not used in datapaths any more,
but is a basic building memory cell
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Sequential Circuits
IEP on Synthesis of Digital Design 2007
Sizing Issues
2.0
3
Q
S
W = 0.5 m m
2
W = 0.6 m m
W = 0.7 m m
Volts
Q (Volts)
1.5
1.0
1
W = 0.8 m m
0.5
0.0
2.0
2.5
3.0
W/L 5 and 6
3.5
4.0
(a)
Output voltage dependence
on transistor width
0
W = 1m m
W = 0.9 m m
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
time (ns)
(b)
Transient response
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Sequential Circuits
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Storage Mechanisms
Dynamic (charge-based)
Static
CLK
CLK
Q
D
Q
CLK
CLK
D
CLK
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Sequential Circuits
IEP on Synthesis of Digital Design 2007
Making a Dynamic Latch Pseudo-Static
CLK
D
D
CLK
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Sequential Circuits
IEP on Synthesis of Digital Design 2007
Other Latches/Registers: C2MOS
CLK
VDD
VDD
M2
M6
M4
CLK
M8
X
D
CLK
M3
M1
Master Stage
Q
CL1
CLK
M7
CL2
M5
Slave Stage
“Keepers” can be added to make circuit pseudo-static
Clocked CMOS
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Sequential Circuits
IEP on Synthesis of Digital Design 2007
Insensitive to Clock-Overlap
0
VDD
VDD
VDD
VDD
M2
M6
M2
M6
M4
0
M8
X
D
Q
X
D
1
M1
M5
(a) (0-0) overlap
M3
Q
1
M1
M7
M5
(b) (1-1) overlap
May have dual edge registers
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Sequential Circuits
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Other Latches/Registers: TSPC
VDD
VDD
VDD
VDD
Out
In
CLK
CLK
In
CLK
CLK
Out
Positive latch
Negative latch
(transparent when CLK= 1) (transparent when CLK= 0)
True Single Phase Clocked Registers (avoids CLK’)
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Including Logic in TSPC
VDD
VDD
VDD
In1
PUN
VDD
In2
Q
In
CLK
CLK
PDN
Q
CLK
CLK
In1
In2
Example: logic inside the latch
AND latch
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Sequential Circuits
IEP on Synthesis of Digital Design 2007
TSPC Register
VDD
M3
CLK
VDD
VDD
M6
M9
Y
D
CLK
M2
M1
X
CLK
M5
M4
Q
Q
CLK
M8
M7
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Sequential Circuits
Pulse-Triggered Latches
An Alternative Approach
IEP on Synthesis of Digital Design 2007
Ways to design an edge-triggered sequential cell:
Master-Slave
Latches
L1
Data
Pulse-Triggered
Latch
L2
D Q
D Q
Clk
Clk
L
Data
Clk
D Q
Clk
Clk
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Sequential Circuits
IEP on Synthesis of Digital Design 2007
Pulsed Latches
VDD
VDD
M3
M6
CLK
VDD
Q
D
CLKG
M2
CLKG
M1
MP
M5
CLKG
X
MN
M4
(a) register
(b) glitch generation
CLK
CLKG
(c) glitch clock
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Pulsed Latches
Hybrid Latch – Flip-flop (HLFF), AMD K-6 and K-7 :
CLK
P1
P3
x
M6
M3
D
M2
M1
Q
P2
CLKD
M5
M4
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IEP on Synthesis of Digital Design 2007
Sequential Circuits
Hybrid Latch-FF Timing
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IEP on Synthesis of Digital Design 2007
CLK
Reference
b
CLK
CLK
log
REG
REG
CLK
REG
CLK
Out
REG
log
REG
b
REG
CLK
a
REG
a
REG
Pipelining
CLK
CLK
Pipelined
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Out
IEP on Synthesis of Digital Design 2007
Sequential Circuits
Latch-Based Pipeline
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Sequential Circuits
IEP on Synthesis of Digital Design 2007
Non-Bistable Sequential Circuits─
Schmitt Trigger
V OH
Vou t
In
Out
•VTC with hysteresis
V OL
•Restores signal slopes
VM–
VM+
Vi n
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IEP on Synthesis of Digital Design 2007
Sequential Circuits
Noise Suppression using Schmitt
Trigger
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Sequential Circuits
IEP on Synthesis of Digital Design 2007
CMOS Schmitt Trigger
VDD
M2
Vin
M4
Vout
X
M1
M3
Moves switching threshold
of the first inverter
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Sequential Circuits
IEP on Synthesis of Digital Design 2007
Schmitt Trigger Simulated VTC
2.5
2.5
2.0
2.0
VM1
1.5
(V)
1.0
X
V
1.5
(V)
1.0
x
V
VM2
0.5
0.0
0.0
k=1
k=3
k=2
0.5
0.5
1.0
1.5
Vin (V)
2.0
2.5
Voltage-transfer characteristics with hysteresis.
k=4
0.0
0.0
0.5
1.0
1.5
Vin (V)
2.0
2.5
The effect of varying the ratio of the
PMOS device M4. The width is k* 0.5m m.
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IEP on Synthesis of Digital Design 2007
CMOS Schmitt Trigger (2)
VDD
M4
M6
M3
In
Out
M2
X
M5
VDD
M1
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Multivibrator Circuits
R
S
Bistable Multivibrator
flip-flop, Schmitt Trigger
T
Monostable Multivibrator
one-shot
Astable Multivibrator
oscillator
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IEP on Synthesis of Digital Design 2007
Transition-Triggered Monostable
In
DELAY
td
Out
td
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Sequential Circuits
IEP on Synthesis of Digital Design 2007
Astable Multivibrators (Oscillators)
0
1
2
N-1
Ring Oscillator
simulated response of 5-stage oscillator
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IEP on Synthesis of Digital Design 2007
Differential Delay Element and VCO
V o2
Sequential Circuits
v3
V o1
v1
in 1
in 2
v2
v
4
V ctrl
delay cell
two stage VCO
3.0
2.5
V1 V2 V3 V4
2.0
1.5
1.0
0.5
0.0
2 0.5
0.5
1.5
2.5
3.5
time (ns)
simulated waveforms of 2-stage VCO
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