Transcript EE19D Topic 6

EE19D Digital Electronics
Sequential Logic: Fundamentals and
Circuits (Part two)
1
Synchronous Sequential Networks
• The block diagram of figure 4 can be modified
to represent a synchronous network by replacing
all the memory elements by Flip-flops which are
controlled by the same clock signal (figure 6).
2
Figure 6: Synchronous sequential network
• All flip-lop changes are assumed to be
synchronized by a single clocking signal and
change their state following the same edge of
the clock. Activity in the network is cyclic with
the clock signal. That activity consists of the
following.
• 1.
Following the synchronizing clock edge:
• (a)
primary input variables W1, W2…….Wn may
change value,
• (b)
flip-flop output variables y1, y2, ……yn may
change value.
3
• But all the changes must take place within a
finite, know interval Tf, usually Tf is the
maximum of the flip-flop propagation delays.
• 2. Then the new input symbol to the
combinational logic, the (n +p)-tuple (W1,
W2….Wn, y1, y2…..yp), propagates through that
logic to form the m output Z1, Z2, …..Zm and the
flip-flop input signals. All these changes must
take place within a finite interval, known as
interval Tg. Tg is the maximum propagation delay
through the combinational logic block.
4
• 3.
Then all the flip-flop input signals must be
held at their final values for an interval equal to
or greater than the setup time Tsu for the flipflops. Only after this interval it is safe to
another synchronizing edge to occur. The clock
period T must therefore satisfy T > Tf + Tg + Tsu
for reliable behaviour in the network.
5
State Model
Figure 7: State Model
6
A synchronous sequential network can be represented in two
different ways (Moore and Mealy)
7
State-machine structure (Mealy)
output depends on
state and input
typically edge-triggered
D flip-flops
8
State-machine structure (Moore)
output depends
on state only
typically edge-triggered
D flip-flops
9
State-machine structure (pipelined)
• Often used in PLD-based state machines.
– Outputs taken directly from flip-flops, valid sooner
after clock edge.
– But the “output logic” must determine output value
one clock tick sooner (“pipelined”).
10
State Diagram
• A state diagram is a directed graph used to
represent the transition and output function in
a sequential system. Each state is represented
by a node and each transition by an arc.
• An arc from node Sk to node Sj and labelled x/z
specifies that, for a present state Sk and an
input x, the next state is Sj and the output is z
(figure 9).
11
x/z
Sj
Sk
State
Figure 9: State Diagram (Mealy)
x
Sk/zk
Sj/zj
State
Figure 10: State diagram (equivalent Moore)
12
A finite state machine can be represented using a state diagram
or a state table. Figure 11 shows different modes of
representation of a Mealy Machine
1/1
S0
0/1
S1
S2
0/0p
1/0
0/0
1/1
a) State diagram
13
Current State S(t)
Input x(t)
0
1
S0
S1,1
S2,1
S1
S1,0
S0,1
S2
S1,0
S2,1
S(t+1),z(t)
b) State stable
14
Present Sate
A
Input
x
Next State
B
NA
Output z
NB
0
0: S0
0
0
1: S1
1
0
0: S0
1
1
0: S2
1
0
1: S1
0
0
1: S1
0
0
1: S1
1
0
0: S0
1
1
0: S2
0
0
1: S1
0
1
0: S2
1
1
0: S2
1
b) State transition table
Figure 12: Different modes of representations of a finite state
machine
15
State-machine analysis steps
• Assumption: Starting point is a logic diagram.
1. Determine next-state function F and output
function G.
2a. Construct state table
– For each state/input combination, determine the
excitation value.
– Using the characteristic equation, determine the
corresponding next-state values (trivial with D f-f’s).
2b. Construct output table
– For each state/input combination, determine the output
value. (Can be combined with state table.)
3. (Optional) Draw state diagram
16
Example state machine
17
Excitation equations
18
Transition equations
• Excitation equations
• Characteristic equations
• Substitute excitation equations into
characteristic equations
19
Transition and state tables
(transition
equations)
(output equation)
transition
table
state table
state/output
table
another name for this function?
20
State diagram
• Circles for states
• Arrows for transitions (note output info)
21
Modified state machine
MAXS
MAXS = Q0  Q1
• Moore machine
22
Updated
state/output
table, state
diagram
23
Timing diagram for state machine
• Not a complete description of machine
behavior
24
c)
Specification of different types
of sequential systems.
We will present two examples of specification of
sequential systems. Additional systems are described in
subsequent chapters.
Modulo-p Counter: A modulo-p counter is a sequential
system whose input is a binary variable and whose output
has integer values from the set {0,1, 2, ……,p-1}. Its
time behaviour is described as follows:
25
A state description requires p states. Assigning the integers 0 to p1 as the state labels, the following description is obtained:
Input: x(t) {0,1}
Output: z(t) {0,1, 2,……,p-1}
State: s(t) {0,1, 2,……,p-1}
Initial state:
s(0) = 0
Function: the transition and output functions are: s(t+1) = [s(t)
+ x(t)] mod p and z(t) = s(t)
Figure 13 shows the state diagram of a modulo-5 counter.
26
Figure 13. State diagram of a modulo-5 counter.
Pattern Recognizer: A pattern recognizer is a sequential system
whose binary output at time t indicates whether the input
subsequence ending at time t corresponds to the particular pattern
recognized by the system. Consequently, a pattern recognizer is a
finite memory system – A sequential system has finite memory of
length m if its output z(t) depends only on the last input values, that
is z(t) = F(x(t-m+1,t)).
27
A sequential system that recognizes the pattern P =
(p0,p1,….,pm-1) has the following description:
Input: x(t) I
Output: z(t) {0,1}
Function :
1 if x(t-m  1 )  P
z (t )  
0 otherwise
28
Algorithmic State Machine (ASM)
• Why State diagrams are not Enough ?
– Not flexible enough for describing very complex
finite state machines
– Not suitable for gradual refinement of finite state
machine
– Do not obviously describe an algorithm: that is, well
specifiedsequence of actions based on input data:
• algorithm = sequencing + data manipulation
• separation of control and data
• Gradual shift towards program-like
representation:
– Algorithm State Machine (ASM) Notation
– Hardware Description Languages (e.g., ABEL, VHDL
or Verilog)
29
30
31
32
33
34
Figure 14: a) State machine; b) its equivalent ASM diagram
35
FSMs and ASMs
Example: Odd Parity Checker
Assert output whenever input bit stream has odd # of 1's
Reset
0
Even
[0]
1
0
1
Odd
[1]
State
Diagram
Present State
Even
Even
Odd
Odd
Input
0
1
0
1
Next St at e
Even
Odd
Odd
Even
Out put
0
0
1
1
Symbolic State Transition Table
Present State
0
0
1
1
Input
0
1
0
1
Next St at e
0
1
1
0
Out put
0
0
1
1
Encoded State Transition Table
36
Example: Odd Parity Checker
Next State/Output Functions
NS = PS xor PI; OUT = PS
Input
NS
Input
D
Q
CLK
R
T
Output
CLK
PS/Output
R
Q
Q
\Reset
\Reset
T FF Implementation
D FF Implementation
Input
Q
1
0
0
1
1
0
1
0
1
1
1
0
Clk
Output
1
1
1
0
1
1
0
0
1
0
1
1
Timing Behavior: Input 1 0 0 1 1 0 1 0 1 1 1 0
37
0
0/ 0
0
0
[0]
0
1/ 0
0/ 0
1
0
1
1
1/ 1
[0]
1
2
FSMs/ASMs (Moore
and Mealy) of the
odd Parity Detector
1
[1]
FSM Diagrams
S0
00
S0
IN
S1
IN
01
IN
S2
0
S1
1
IN
10
H.OUT
IN
H.OUT
ASM Diagrams
38
Concept of the Synchronous Sequential Circuit
Timing: When are inputs sampled, next state computed, outputs asserted?
State Time: Time between clocking events
• Clocking event causes state/outputs to transition, based on inputs
• For set-up/hold time considerations:
Inputs should be stable before clocking event
• After propagation delay, Next State entered, Outputs are stable
NOTE: Asynchronous signals take effect immediately
Synchronous signals take effect at the next clocking event
E.g., tri-state enable: effective immediately
sync. counter clear: effective at next clock event
39
Example: Positive Edge Triggered Synchronous System
•
State Time
•
•
– affect datapath immediately
– could cause inputs from datapath
to change
Cloc k
•
Inputs
On rising edge, inputs sampled;
outputs, next state computed
After propagation delay, outputs
and next state are stable
Immediate Outputs:
Delayed Outputs:
– take effect on next clock edge
– propagation delays must exceed
hold times
Outputs
40
Example: Vending Machine SSC
General Machine Concept:
deliver package of gum after 15 cents deposited
single coin slot for dimes, nickels
no change
Step 1. Understand the problem:
Draw a picture!
N
Block Diagram
Coin
Sensor
D
Reset
Vending
Machine
SSC
Open
Gum
Release
Mechanism
Clk
41
Vending Machine Example
Step 2. Map into more suitable abstract representation
Tabulate typical input sequences:
three nickels
nickel, dime
dime, nickel
two dimes
two nickels, dime
Reset
S0
N
S1
D
S2
Draw state diagram:
N
Inputs: N, D, reset
D
N
D
S4
S5
S6
[open]
[open]
[open]
S3
Output: open
N
D
S7
S8
[open]
[open]
42
Step 3: State Minimization
Pres ent
State
Reset
0¢
0¢
N
5¢
D
5¢
N
10¢
D
N, D
10¢
15¢
[o pen]
15¢
reuse states
whenever
possible
Inputs
D N
0
0
1
1
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
0
1
X
Next
State
Output
Open
0¢
5¢
10¢
X
5¢
10¢
15¢
X
10¢
15¢
15¢
X
15¢
0
0
0
X
0
0
0
X
0
0
0
X
1
Symbolic State Table
43
Step 4: State Encoding
Present State
Q1 Q0
0
0
0
1
1
0
1
1
Inputs
D N
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Next State
D1 D0
Output
Open
0 0
0 1
1 0
X X
0 1
1 0
1 1
X X
1 0
1 1
1 1
X X
1 1
1 1
1 1
X X
0
0
0
X
0
0
0
X
0
0
0
X
1
1
1
X
44
Parity Checker Example
Step 5. Choose FFs for implementation
Q1 Q0
00
DN
Q1
01
11
10
00
0
0
1
1
01
0
1
1
1
11
D
10
Q1 Q0
00
DN
1
1
1
Q0
N
D1 D
CLK
0
01
1
0
1
1
10
Q1
D
X X
X X
0
1
1
1
Q1 Q0
00
DN
Q
Q1
RQ
\ Q1
Q1
01
11
10
00
0
0
1
0
01
0
0
1
0
N
11
X X X X
10
0
D
Q0
0
1
N
0
Q0
D1 = Q1 + D + Q0 N
\res et
Q1
N
10
1
D
N
\ Q0
Q0
\N
11
1
Q0
Q1
D
01
0
11
1
Q1
00
N
X X X X
D FF easiest to use
OPEN
D0 = N Q0 + Q0 N + Q1 N + Q1 D
D0 D
Q
CLK
R
\res et
Q0
OPEN = Q1 Q0
Q \ Q0
8 Gates
45
Parity Checker Example
Step 5. Choosing FF for Implementation
J-K FF
Pres ent State
Q1 Q0
0
0
0
1
1
0
1
1
Inputs
D N
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Next State J1
D 1 D0
0
0
1
X
0
1
1
X
1
1
1
X
1
1
1
X
0
1
0
X
1
0
1
X
0
1
1
X
1
1
1
X
0
0
1
X
0
1
1
X
X
X
X
X
X
X
X
X
K1
J0 K 0
X
X
X
X
X
X
X
X
0
0
0
X
0
0
0
X
0
1
0
X
X
X
X
X
0
1
1
X
X
X
X
X
X
X
X
X
0
1
0
X
X
X
X
X
0
0
0
X
Remapped encoded state transition table
46
Moore and Mealy Machines
State Diagram Equivalents
Moore
Machine
N D + Reset
(N D + Reset)/ 0
Reset/0
Reset
0¢
0¢
Mealy
Machine
[0]
Reset/0
Reset
N/0
5¢
5¢
N D/ 0
N
D/0
ND
D
[0]
N
N/0
10¢
10¢
D
D/1
N D/ 0
N+D/1
[0]
N+D
ND
15¢
15¢
Reset/1
Outputs are associated
with State
[1]
Reset
Outputs are associated
with Transitions
47
ASM Chart for Vending Machine
0¢
00
10¢
T
D
10
T
D
F
F
F
F
N
N
T
5¢
T
15¢
01
11
H.Open
T
N
F
F
D
Res et
F
T
T
0¢
48
Another design example (from text: pp. 564 - 576)
• Design a machine with inputs A and B and output
Z that is 1 if:
– A had the same value at the two previous ticks
– B has been 1 since the last time the above was true
49
State assignment
• There are 6,720 different state assignments of
5 states to 3 variables.
– And there are even more using 4 or more variables
• Here are a few “obvious” or “interesting” ones:
50
Transition/output table
(decomposed assignment)
• Simple textual substitution
• With D flip-flops, excitation table is identical to
transition table.
51
VHDL Coding: One "State" Process
FSM_FF: process (CLK, RESET)
begin
if RESET='1' then
STATE <= START ;
elsif CLK'event and CLK='1' then
case STATE is
when START => if X=GO_MID then
STATE <= MIDDLE ;
end if ;
when MIDDLE => if X=GO_STOP then
STATE <= STOP ;
end if ;
when STOP => if X=GO_START then
STATE <= START ;
end if ;
when others => STATE <= START ;
end case ;
end if ;
end process FSM_FF ;
52
VHDL Coding: Two "State" Processes
FSM_FF: process (CLK, RESET) begin
if RESET='1' then
STATE <= START ;
elsif CLK'event and CLK='1' then
STATE <= NEXT_STATE ;
end if;
end process FSM_FF ;
FSM_LOGIC: process ( STATE , X)
begin
NEXT_STATE <= STATE ;
case STATE is
when START => if X=GO_MID then
NEXT_STATE <= MIDDLE ;
end if ;
when MIDDLE => ...
when others => NEXT_STATE <= START ;
end case ;
end process FSM_LOGIC ;
53
Finite State Machine Word Problems
Mapping English Language Description to Formal Specifications
Four Case Studies:
Finite String Pattern Recognizer
Complex Counter with Decision Making
Traffic Light Controller
Digital Combination Lock
T-bird tail-lights example
We will use state diagrams and ASM Charts
54
Develop
excitation
equations
• Assume unused states have next-state = 000
55
Finite String Pattern Recognizer
A finite string recognizer has one input (X) and one output (Z).
The output is asserted whenever the input sequence …010…
has been observed, as long as the sequence 100 has never been
seen.
Step 1. Understanding the problem statement
Sample input/output behavior:
X: 00101010010
Z: 00010101000
X: 11011010010
Z: 00000001000
56
Finite String Recognizer
Step 2. Draw State Diagrams/ASM Charts for the strings that must be
recognized. I.e., 010 and 100.
The output is asserted whenever the input sequence ..010… has
been observed, as long as the sequence 100 has never been seen.
Moore State Diagram
Reset signal places
FSM in S0
Outputs 1
Loops in State
57
Finite String Recognizer
Exit conditions from state S3:
if next input is 0 then have …0100 (state S6)
if next input is 1 then have …0101 (state S2)
58
Finite String Recognizer
Exit conditions from S1: recognizes strings of form …0 (no 1 seen)
loop back to S1 if input is 0
Exit conditions from S4: recognizes strings of form …1 (no 0 seen)
loop back to S4 if input is 1
59
Finite String Recognizer
S2, S5 with incomplete transitions
S2 = …01; If next input is 1, then string could be prefix of (01)1(00)
S4 handles just this case!
S5 = …10; If next input is 1, then string could be prefix of (10)1(0)
S2 handles just this case!
Final State Diagram
60
Finite String Recognizer
Review of Process:
Write down sample inputs and outputs to understand specification
Write down sequences of states and transitions for the sequences
to be recognized
Add missing transitions; reuse states as much as possible
Verify I/O behavior of your state diagram to insure it functions
like the specification
61
Complex Counter
A sync. 3 bit counter has a mode control M. When M = 0, the counter
counts up in the binary sequence. When M = 1, the counter advances
through the Gray code sequence.
Binary: 000, 001, 010, 011, 100, 101, 110, 111
Gray: 000, 001, 011, 010, 110, 111, 101, 100
Valid I/O behavior:
Mode Input M
0
0
1
1
1
0
0
Current State
000
001
010
110
111
101
110
Next State (Z2 Z1 Z0)
001
010
110
111
101
110
111
62
Complex Counter
One state for each output combination
Add appropriate arcs for the mode control
S0
000
S1
001
H.Z 0
0
S2
1
M
010
H.Z 1
M
S3
011
H.Z 1
H.Z 0
0
1
M
1
S6
0
110
S4
H.Z 2
H.Z 1
S7
111
M
1
M
H.Z 2
H.Z 1
H.Z 0
0
100
H.Z 2
0
S5
101
H.Z 2
H.Z 0
1
0
M
63
1
Traffic Light Controller
A busy highway is intersected by a little used farmroad. Detectors
C sense the presence of cars waiting on the farmroad. With no car
on farmroad, light remain green in highway direction. If vehicle on
farmroad, highway lights go from Green to Yellow to Red, allowing
the farmroad lights to become green. These stay green only as long
as a farmroad car is detected but never longer than a set interval.
When these are met, farm lights transition from Green to Yellow to
Red, allowing highway to return to green. Even if farmroad vehicles
are waiting, highway gets at least a set interval as green.
Assume you have an interval timer that generates a short time pulse
(TS) and a long time pulse (TL) in response to a set (ST) signal. TS
is to be used for timing yellow lights and TL for green lights.
64
Traffic Light Controller
Picture of Highway/Farmroad Intersection:
Farmroad
C
HL
FL
Highway
Highway
HL
FL
C
Farmroad
65
Traffic Light Controller
Tabulation of Inputs and Outputs:
Input Signal
reset
C
TS
TL
Description
place FSM in initial state
detect vehicle on farmroad
short time interval expired
long time interval expired
Output Signal
HG, HY, HR
FG, FY, FR
ST
Description
assert green/yellow/red highway lights
assert green/yellow/red farmroad lights
start timing a short or long interval
Tabulation of Unique States: Some light configuration imply others
State
S0
S1
S2
S3
Description
Highway green (farmroad red)
Highway yellow (farmroad red)
Farmroad green (highway red)
Farmroad yellow (highway red)
66
Traffic Light Controller
Refinement of ASM Chart:
Start with basic sequencing and outputs:
S0
H.HG
H.FR
S1
H.HY
H.FR
S3
H.HR
H.FY
S2
H.HR
H.FG
67
Traffic Light Controller
Determine Exit Conditions for S0:
Car waiting and Long Time Interval Expired- C · TL
S0
S0
H.HG
H.FR
H.HG
H.FR
C · TL
0
0
TL
T L • C
1
0
C
1
H.ST
1
H.ST
S1
H.HY
H.FR
S1
H.HY
H.FR
Equivalent ASM Chart Fragments
68
Traffic Light Controller
S1 to S2 Transition:
Set ST on exit from S0
Stay in S1 until TS asserted
Similar situation for S3 to S4 transition
S1
H.HY
H.FR
0
TS
H.ST
S2
H.HR
H.FG
1
69
Traffic Light Controller
S2 Exit Condition: no car waiting OR long time interval expired
S0
H.HG
H.FR
0
H.ST
1
T L • C S3
H.HR
H.FY
TS
0
1
H.ST
S1
H.HY
H.FR
0
TS
H.ST
H.ST
1
S2
H.HR
H.FG
0
TL + C
1
Complete ASM Chart for Traffic Light Controller
70
Traffic Light Controller
Compare with state diagram:
TL + C
Reset
S0: HG
S0
TL•C/ST
S1: HY
TS/ST
TS
S1
S2: FG
S3
TS
TS/ST
S3: FY
TL + C/ST
S2
TL • C
Advantages of ASM Charts:
Concentrates on paths and conditions for exiting a state
Exit conditions built up incrementally, later combined into
single Boolean condition for exit
Easier to understand the design as an algorithm
71
Digital Combination Lock
"3 bit serial lock controls entry to locked room. Inputs are RESET,
ENTER, 2 position switch for bit of key data. Locks generates an
UNLOCK signal when key matches internal combination. ERROR
light illuminated if key does not match combination. Sequence is:
(1) Press RESET, (2) enter key bit, (3) Press ENTER, (4) repeat (2) &
(3) two more times."
Problem specification is incomplete:
how do you set the internal combination?
exactly when is the ERROR light asserted?
Make reasonable assumptions:
hardwired into next state logic vs. stored in internal register
assert as soon as error is detected vs. wait until full combination
has been entered
Our design: registered combination plus error after full combination
72
Digital Combination Lock
Understanding the problem: draw a block diagram
RESET
Operator Data
ENT ER
UNLOCK
KEY-IN
Combi nation
Loc k FSM ERROR
Internal
Combination
L0
L1
L2
Inputs:
Reset
Enter
Key-In
L0, L1, L2
Outputs:
Unlock
Error
73
Digital Combination Lock
Enumeration of states:
what sequences lead to opening the door?
error conditions on a second pass
START state plus three key COMParison states
START
START entered on RESET
Exit START when ENTER is pressed
1
Res et
0
Enter
COMP0
0
1
KI = L0
Y
N
Continue on if Key-In matches L0
74
Digital Combination Lock
COMP0
IDLE1
Path to unlock:
KI = L 0
N
Y
Enter
1
COMP2
IDLE0
0
Wait for
Enter Key press
Enter
COMP1
0
KI = L2
N
Y
1
DONE
H.Unlock
Compare Key-IN
KI = L1
Y
N
Res et
0
1
START
75
Digital Combination Lock
Now consider error paths
Should follow a similar sequence as UNLOCK path, except
asserting ERROR at the end:
IDLE0'
ERROR3
IDLE1'
H.Error
Enter
ERROR1
1
0
Enter
ERROR2
0
Res et
0
1
1
START
COMP0 error exits to IDLE0'
COMP1 error exits to IDLE1'
COMP2 error exits to ERROR3
76
Reset + Ent er
Digital Combination Lock
Reset
Start
Reset • Enter
Comp0
KI = L0
KI ° L0
Ent er
Ent er
Idle0
Idle0'
Ent er
Ent er
Comp1
Equivalent State Diagram
KI = L1
Error1
KI ° L1
Ent er
Ent er
Idle1
Idle1'
Ent er
Ent er
Comp2
KI = L2
Reset
Done
[Unlock]
Reset
Start
Error2
KI ° L2
Error3
[Error]
Reset
Reset
Start
77
T-bird tail-lights (text, pp585 – 591)
78
State
diagram
Inputs:
LEFT, RIGHT, HAZ
Outputs:
Six lamps
(function of state only
79