Transcript Chapter #8: Finite State Machine Design Contemporary Logic

Introduction
Chapter #8: Finite State Machine Design
8-1
Motivation
Introduction
• Counters: Sequential Circuits where State = Output
• Generalizes to Finite State Machines:
Outputs are Function of State (and Inputs)
Next States are Functions of State and Inputs
Used to implement circuits that control other circuits
"Decision Making" logic
• Application of Sequential Logic Design Techniques
Word Problems
Mapping into formal representations of FSM behavior
Case Studies
8-2
Chapter Overview
Introduction
Concept of the State Machine
• Partitioning into Datapath and Control
• When Inputs are Sampled and Outputs Asserted
Basic Design Approach
• Six Step Design Process
Alternative State Machine Representations
• State Diagram, ASM Notation, VHDL, ABEL Description Language
Moore and Mealy Machines
• Definitions, Implementation Examples
Word Problems
• Case Studies
8-3
Introduction
Concept of the State Machine
Computer Hardware = Datapath + Control
Qualifiers
Registers
Combinational Functional
Units (e.g., ALU)
Busses
Control
Control
FSM generating sequences
of control signals
Instructs datapath what to
do next
"Puppeteer who pulls the
strings"
State
Control
Signal
Outputs
Qualifiers
and
Inputs
"Puppet"
Datapath
8-4
Introduction
Concept of the State Machine
Example: Odd Parity Checker
Assert output whenever input bit stream has odd # of 1's
Reset
0
Even
[0]
1
0
1
Odd
[1]
State
Diagram
Present State
Even
Even
Odd
Odd
Input
0
1
0
1
Next St at e
Even
Odd
Odd
Even
Out put
0
0
1
1
Symbolic State Transition Table
Present State
0
0
1
1
Input
0
1
0
1
Next St at e
0
1
1
0
Out put
0
0
1
1
Encoded State Transition Table
8-5
Introduction
Concept of the State Machine
Example: Odd Parity Checker
Next State/Output Functions
NS = PS xor PI; OUT = PS
Input
NS
Input
D
Q
CLK
R
Q
CLK
PS/Output
R
Q
Q
\Reset
\Reset
T FF Implementation
D FF Implementation
Input
T
Output
1
0
0
1
1
0
1
0
1
1
1
0
Clk
Output
1
1
1
0
1
1
0
0
1
0
1
1
Timing Behavior: Input 1 0 0 1 1 0 1 0 1 1 1 0
8-6
Concept of State Machine
Introduction
Timing:
When are inputs sampled, next state computed, outputs asserted?
State Time: Time between clocking events
• Clocking event causes state/outputs to transition, based on inputs
• For set-up/hold time considerations:
Inputs should be stable before clocking event
• After propagation delay, Next State entered, Outputs are stable
NOTE: Asynchronous signals take effect immediately
Synchronous signals take effect at the next clocking event
E.g., tri-state enable: effective immediately
sync. counter clear: effective at next clock event
8-7
Concept of State Machine
Introduction
Example: Positive Edge Triggered Synchronous System
State Time
Cloc k
On rising edge, inputs sampled
outputs, next state computed
After propagation delay, outputs and
next state are stable
Inputs
Immediate Outputs:
affect datapath immediately
could cause inputs from datapath to change
Outputs
Delayed Outputs:
take effect on next clock edge
propagation delays must exceed hold times
8-8
Introduction
Concept of the State Machine
Communicating State Machines
One machine's output is another machine's input
X
CLK
FSM 2
FSM 1
Y
FSM 1
A
A
B
C
D
D
X
Y=0
Y=0
X=0
X=0
A
[1]
FSM 2
C
[0]
X=1
Y=1
Y
X=1
Y=0,1
B
[0]
X=0
D
[1]
Machines advance in lock step
Initial inputs/outputs: X = 0, Y = 0
8-9
Basic Design Approach
Six Step Process
Introduction
1. Understand the statement of the Specification
2. Obtain an abstract specification of the FSM
3. Perform a state mininimization
4. Perform state assignment
5. Choose FF types to implement FSM state register
6. Implement the FSM
1, 2 covered now; 3, 4, 5 covered later;
4, 5 generalized from the counter design procedure
8-10
Introduction
Basic Design Approach
Example: Vending Machine FSM
General Machine Concept:
deliver package of gum after 15 cents deposited
single coin slot for dimes, nickels
no change
Step 1. Understand the problem:
Draw a picture!
Block Diagram
N
Coin
Sensor D
Reset
Vending
Machine
FSM
Open
Gum
Release
Mechani sm
Clk
8-11
Introduction
Vending Machine Example
Step 2. Map into more suitable abstract representation
Tabulate typical input sequences:
three nickels
nickel, dime
dime, nickel
two dimes
two nickels, dime
Reset
S0
N
Draw state diagram:
S1
Inputs: N, D, reset
Output: open
N
D
S2
N
D
S4
S5
S6
[open]
[open]
[open]
S3
N
D
D
S7
S8
[open]
[open]
8-12
Introduction
Vending Machine Example
Step 3: State Minimization
Present
State
Reset
0¢
0¢
N
5¢
D
5¢
N
10¢
D
N, D
15¢
10¢
[open]
reuse states
whenever
possible
15¢
Inputs
D N
0
0
1
1
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
0
1
X
Next
State
Output
Open
0¢
5¢
10¢
X
5¢
10¢
15¢
X
10¢
15¢
15¢
X
15¢
0
0
0
X
0
0
0
X
0
0
0
X
1
Symbolic State Table
8-13
Introduction
Vending Machine Example
Step 4: State Encoding
Present State Inputs
Q1 Q0
D N
0
0
0
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Next State
D1 D0
0
0
1
X
0
1
1
X
1
1
1
X
1
1
1
X
0
1
0
X
1
0
1
X
0
1
1
X
1
1
1
X
Output
Open
0
0
0
X
0
0
0
X
0
0
0
X
1
1
1
X
8-14
Introduction
Parity Checker Example
Step 5. Choose FFs for implementation
Q1 Q0
00
DN
00 0
01 0
D
11 X
10 1
D FF easiest to use
Q1
Q1
Q1 Q0
00 01 11 10
01 11 10
DN
0 1 1
00 0 1 1 0
01 1 0 1 1
1 1 1
N
11 X X X X
X X X
D
10 0 1 1 1
1 1 1
Q0
N
D1 D Q Q 1
CLK
\ Q1
RQ
Q1
N
Q1
D
D
0
1
0
11 X
X
X
X
10 0
0
1
0
N
Q0
K-map for Open
D1 = Q1 + D + Q0 N
D0 = N Q0 + Q0 N + Q1 N + Q1 D
\res et
N
\ Q0
Q0
\N
N
01 0
Q0
K-map for D0
Q0
K-map for D1
Q1
D
Q1
Q1 Q 0
00 01 11 10
DN
00 0 0 1 0
OPEN
OPEN = Q1 Q0
D0 D Q
CLK
R
\res et
Q0
Q \ Q0
8 Gates
8-15
Introduction
Parity Checker Example
Step 5. Choosing FF for Implementation
J-K FF
Pres ent State
Q1 Q0
0
0
0
1
1
0
1
1
Inputs
D N
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Next State J1
D 1 D0
0
0
1
X
0
1
1
X
1
1
1
X
1
1
1
X
0
1
0
X
1
0
1
X
0
1
1
X
1
1
1
X
0
0
1
X
0
1
1
X
X
X
X
X
X
X
X
X
K1
J0 K 0
X
X
X
X
X
X
X
X
0
0
0
X
0
0
0
X
0
1
0
X
X
X
X
X
0
1
1
X
X
X
X
X
X
X
X
X
0
1
0
X
X
X
X
X
0
0
0
X
Remapped encoded state transition table
8-16
Introduction
Vending Machine Example
Implementation:
Q1
Q1 Q0
00 01 11 10
DN
00 0 0 1 1
D
01 0
1
1
1
11 X
X
X
X
10 1
1
1
1
Q0
K-map for D1
Q1
Q1 Q0
00 01 11 10
DN
00 0 0 1 1
D
01 0
1
1
1
11 X
X
X
X
10 1
1
1
1
Q0
K-map for D1
Q1
Q1 Q0
00 01 11 10
DN
00 0 0 1 1
N
D
01 0
1
1
1
11 X
X
X
X
J1 = D + Q0 N
K1 = 0
N
J0 = Q0 N + Q1 D
10 1
1
1
1
K0 = Q1 N
Q0
K-map for D1
Q1
Q 1 Q0
N
Q0
00 01 11 10
D
DN
0
0
1
1
\ Q0
00
N
01 0 1 1 1
N Q
1
11 X X X X
N
D
D
10 1 1 1 1
J
CLK
K RQ
Q1
\ Q1
OPEN
CLK
\ Q1
J
Q
KR Q
N
Q0
K-map for D1
Q
\res et
Q0
\ Q0
7 Gates
8-17
Alternative State Machine Representations
Introduction
Why State Diagrams Are Not Enough
Not flexible enough for describing very complex finite state machines
Not suitable for gradual refinement of finite state machine
Do not obviously describe an algorithm: that is, well specified
sequence of actions based on input data
algorithm = sequencing + data manipulation
separation of control and data
Gradual shift towards program-like representations:
• Algorithmic State Machine (ASM) Notation
• Hardware Description Languages (e.g., VHDL)
8-18
Introduction
Alternative State Machine Representations
Algorithmic State Machine (ASM) Notation
Three Primitive Elements:
• State Box
• Decision Box
• Output Box
State Machine in one state
block per state time
Single Entry Point
Unambiguous Exit Path
for each combination
of inputs
Outputs asserted high (.H)
or low (.L); Immediate (I)
or delayed til next clock
State
Ent ry Pat h
State Code
*
State
Name
State
Out put List
T
***
State Box
Condit ion
Condit ion
Box
Condit ional
Out put List
F
ASM
Bl ock
Out put
Box
Exit s to
other ASM Blocks
8-19
Introduction
Alternative State Machine Representations
ASM Notation
Condition Boxes:
Ordering has no effect on final outcome
Equivalent ASM charts:
A exits to B on (I0=1 & I1=1) else exit to C
A
A
010
I0
T
010
F
I1
T
F
I1
F
F
I0
T
T
B
C
B
C
8-20
Alternative State Machine Representations
Example: Parity Checker
Introduction
Input X, Output Z
Even
0
Nothing in output list implies Z not asserted
Z asserted in State Odd
F
X
T
Odd
Present Next
Input State
State Output
F
Even
Even Not A
T
Even
Odd Not A
F
A
Odd
Odd
T
A
Odd
Even
1
H.Z
F
X
Symbolic State Table:
T
Trace paths to derive
state transition tables
Encoded State Table:
Present Next
Input State
State Output
0
0
0
0
1
0
0
1
0
1
1
1
1
1
1
0
8-21
Introduction
Alternative State Machine Representations
ASM Chart for Vending Machine
0¢
00
10¢
T
D
10
T
D
F
F
F
F
N
N
T
5¢
T
15¢
01
11
H.Open
T
N
F
F
D
Reset
F
T
T
0¢
8-22
Alternative State Machine Representations
Hardware Description Languages: VHDL
ENTITY parity_checker IS
PORT (
x, clk: IN BIT;
z: OUT BIT);
END parity_checker;
Introduction
Interface Description
Architectural Body
ARCHITECTURE behavioral OF parity_checker IS
BEGIN
main: BLOCK (clk = ‘1’ and not clk’STABLE)
TYPE state IS (Even, Odd);
SIGNAL state_register: state := Even;
BEGIN state_even:
BLOCK ((state_register = Even) AND GUARD)
BEGIN
state_register <= Odd WHEN x = ‘1’
ELSE Even
END BLOCK state_even;
Guard Expression
that evaluates to true
whenever the clock signal
has recently undergone
0 to 1 transition
Determine New State
BEGIN state_odd:
BLOCK ((state_register = Odd) AND GUARD)
BEGIN
state_register <= Even WHEN x = ‘1’
ELSE Odd;
END BLOCK state_odd;
z <= ‘0’ WHEN state_register = Even ELSE
‘1’ WHEN state_register = Odd;
END BLOCK main;
END behavioral;
Determine Outputs
8-23
Alternative State Machine Representations
ABEL Hardware Description Language
Introduction
module parity
test_vectors ([clk, RESET, X] -> [SREG])
title 'odd parity checker state machine'
[0,1,.X.] -> [S0];
u1 device 'p22v10';
[.C.,0,1] -> [S1];
[.C.,0,1] -> [S0];
"Input Pins
[.C.,0,1] -> [S1];
clk, X, RESET pin 1, 2, 3;
[.C.,0,0] -> [S1];
[.C.,0,1] -> [S0];
"Output Pins
[.C.,0,1] -> [S1];
Q, Z
pin 21, 22;
[.C.,0,0] -> [S1];
[.C.,0,0] -> [S1];
Q, Z
istype 'pos,reg';
[.C.,0,0] -> [S1];
end parity;
"State registers
SREG = [Q, Z];
S0 = [0, 0]; " even number of 0's
S1
= [1, 1]; " odd number of 0's
equations
[Q.ar, Z.ar] = RESET; "Reset to state S0
state_diagram SREG
state S0:
if X then S1
else S0;
state S1:
if X then S0
else S1;
8-24
Moore and Mealy Machine Design Procedure
Introduction
Definitions
Moore Machine
Xi
Inputs
Zk
Outputs
Combinational
Logic for
Outputs and
Next State
State Register
Clock
Outputs are function
solely of the current
state
Outputs change
synchronously with
state changes
State
Feedback
State
Register
Xi
Inputs
Combinational
Logic for
Next State
(Flip-flop
Inputs)
Zk
Outputs
Clock
state
feedback
Mealy Machine
Comb.
Logic for
Outputs
Outputs depend on
state AND inputs
Input change causes
an immediate output
change
Asynchronous signals
8-25
Introduction
Moore and Mealy Machines
State Diagram Equivalents
Mealy
Machine
N D + Reset
(N D + Reset)/ 0
Reset/0
Moore
Machine
Reset
0¢
0¢
[0]
Reset/0
Reset
N/0
5¢
5¢
N D/ 0
N
D/0
ND
D
[0]
N
N/0
10¢
10¢
D
D/1
N D/ 0
N+D/1
[0]
N+D
ND
15¢
15¢
Reset/1
Outputs are associated
with State
[1]
Reset
Outputs are associated
with Transitions
8-26
Introduction
Moore and Mealy Machines
States vs. Transitions
Mealy Machine typically has fewer states than Moore Machine
for same output sequence
0
0/ 0
0
0
[0]
Same I/O behavior
0
0
1
Different # of states
1/ 0
0/ 0
1
1
1/ 1
[0]
1
2
S0
[1]
00
S0
0
F
F
IN
IN
T
S1
T
01
S1
1
F
IN
IN
T 10
S2
IN
F
Equivalent
ASM Charts
T
H.OUT
H.OUT
F
1
T
8-27
Introduction
Moore and Mealy Machines
Timing Behavior of Moore Machines
Reverse engineer the following:
X
X
\B
J Q
C
KR Q
FFa
A
\A
Input X
Output Z
State A, B = Z
\Reset
Clk
X
X
\A
J Q
C
KR Q
FFb
Z
\B
\Reset
Two Techniques for Reverse Engineering:
• Ad Hoc: Try input combinations to derive transition table
• Formal: Derive transition by analyzing the circuit
8-28
Introduction
Moore and Mealy Machines
Ad Hoc Reverse Engineering
Behavior in response to input sequence 1 0 1 0 1 0:
100
X
Clk
A
Z
\Res et
Res et X = 1
X=0
X=1
X= 0
X=1
X= 0
X= 0
AB = 00 AB = 00 AB = 11 AB = 11 AB = 10 AB = 10 AB = 01 AB = 00
A B
0 0
Partially Derived
State Transition
Table
0 1
1 0
1 1
X
0
1
0
1
0
1
0
1
A+ B+
? ?
1 1
0 0
? ?
1 0
0 1
1 1
1 0
Z
0
0
1
1
0
0
1
1
8-29
Introduction
Moore and Mealy Machines
Formal Reverse Engineering
Derive transition table from next state and output combinational
functions presented to the flipflops!
Ka = X • B
Kb = X xor A
Ja = X
Jb = X
Z=B
FF excitation equations for J-K flipflop:
A+ = Ja • A + Ka • A = X • A + (X + B) • A
B+ = Jb • B + Kb • B = X • B + (X • A + X • A) • B
Next State K-Maps:
AB
00
X
0
0
1
X
0
1
01
11
10
0
1
1
1
1
1
0
AB
00
01
11
10
0
0
1
0
1
1
O
1
A+
State 00, Input 0 -> State 00
State 01, Input 1 -> State 01
B+
8-30
Introduction
Moore and Mealy Machines
Complete ASM Chart for the Mystery Moore Machine
00
S0
11
S3
H.Z
0
1
X
0
X
1
S1
01
S2
10
H.Z
0
X
1
1
X
0
Note: All Outputs Associated With State Boxes
No Separate Output Boxes , Intrinsic in Moore Machines
8-31
Introduction
Moore and Mealy Machines
Reverse Engineering a Mealy Machine
Clk
D
A
Q
DA
C
\A
X
\A
R
\X
Q
J
C
K
\Res et
A
X
DA
B
Q
R
Q
\B
\Res et
\X
B
B
Z
\X
X
A
Input X, Output Z, State A, B
State register consists of D FF and J-K FF
8-32
Introduction
Moore and Mealy Machine
Ad Hoc Method
Signal Trace of Input Sequence 101011:
100
Note glitches
in Z!
X
Clk
Outputs valid at
following falling
clock edge
A
B
Z
\Res et
Res et
AB=00
Z =0
X =1
AB=00
Z =0
X =0
AB=00
Z =0
X =1
AB=01
Z =0
X =0
AB=11
Z=1
A B
0 0
Partially completed
state transition table
based on the signal
trace
0 1
1 0
1 1
X
0
1
0
1
0
1
0
1
X =1
AB=10
Z =1
A+
0
0
?
1
?
0
1
?
X =1
AB=01
Z =0
B+
1
0
?
1
?
1
0
?
Z
0
0
?
0
?
1
1
?
8-33
Introduction
Moore and Mealy Machines
Formal Method
A+ = B • (A + X) = A • B + B • X
B+ = Jb • B + Kb • B = (A xor X) • B + X • B
=A•B•X + A•B•X + B•X
AB
X
0
Z
=A•X + B•X
00
01
11
10
0
0
1
0
A+
1
0
1
1
0
AB
00
01
11
10
0
1
0
0
0
1
0
1
1
1
AB
00
01
11
10
0
1
1
0
X
X
0
Missing Transitions and Outputs:
State 01, Input 0 -> State 01, Output 1
State 10, Input 0 -> State 00, Output 0
State 11, Input 1 -> State 11, Output 1
A+
Z
1
0
0
1
1
8-34
Introduction
Moore and Mealy Machines
ASM Chart for Mystery Mealy Machine
S0 = 00, S1 = 01, S2 = 10, S3 = 11
S0
1
H. Z
00
10
S2
0
X
0
S1
X
1
H. Z
S3
01
11
H.Z
0
X
1
1
X
0
NOTE: Some Outputs in Output Boxes as well as State Boxes
This is intrinsic in Mealy Machine implementation
8-35
Moore and Mealy Machines
Introduction
States, Transitions, and Outputs in Mealy and Moore Machines
M inputs and N outputs with L flip-flops
- 1 to 2L valid states
max and min state transitions that can an begin in a given state if we include exit transition
- both 2M states
max or min state transitions that can end in a given state
- min : 0 (start up states reachable only on reset)
- max : 2L x 2M states (# of possible input comb. multiplied by # of states)
min and max # of patterns that can be observed on the machine’s outputs
- min : L (every state and every transition can be associated with the
same pattern)
- max depends on the kinds of machine
Mealy : smaller of (2M x 2L, 2N)
Moore : smaller of (2L, 2N)
8-36
Introduction
Moore and Mealy Machines
Synchronous Mealy Machine
Clock
Xi
Inputs
Zk
Outputs
Combinational
Logic for
Outputs and
Next State
State Register
Clock
state
feedback
latched state AND outputs
avoids glitchy outputs! (less hardware)
Use output flip-flops
8-37
Finite State Machine Word Problems
Introduction
Mapping English Language Description to Formal Specifications
Four Case Studies:
• Finite String Pattern Recognizer
• Complex Counter with Decision Making
• Traffic Light Controller
• Digital Combination Lock
We will use state diagrams and ASM Charts
8-38
Finite State Machine Word Problems
Finite String Pattern Recognizer
Introduction
A finite string recognizer has one input (X) and one output (Z).
The output is asserted whenever the input sequence …010…
has been observed, as long as the sequence 100 has never been
seen.
Step 1. Understanding the problem statement
Sample input/output behavior:
X: 00101010010…
Z: 00010101000…
X: 11011010010…
Z: 00000001000…
8-39
Finite State Machine Word Problems
Introduction
Finite String Recognizer
Step 2. Draw State Diagrams/ASM Charts for the strings that must be
recognized. I.e., 010 and 100.
0
S1
[0]
S0
[0]
Reset
Moore State Diagram
Reset signal places
FSM in S0
1
S4
[0]
1
0
S2
[0]
S5
[0]
0
Outputs 1
0
S3
[1]
S6
[0]
0,1
Loops in State
8-40
Introduction
Finite State Machine Word Problems
Finite String Recognizer
Exit conditions from state S3: have recognized …010
if next input is 0 then have …0100!
if next input is 1 then have …0101 = …01 (state S2)
0
S0
[0]
Reset
1
S4
[0]
S1
[0]
1
0
S2
[0]
...01
S5
[0]
0
0
1
S3
[1]
...010
S6
[0]
0
0,1
...100
8-41
Introduction
Finite State Machine Word Problems
Finite String Recognizer
Exit conditions from S1: recognizes strings of form …0 (no 1 seen)
loop back to S1 if input is 0
Exit conditions from S4: recognizes strings of form …1 (no 0 seen)
loop back to S4 if input is 1
0
S0
[0]
Reset
1
S4
[0]
S1
[0]
0
...0
1
0
S2
[0]
...01
0
...010
S5
[0]
1
S3
[1]
1
0
S6
[0]
0
0,1
...100
8-42
Introduction
Finite State Machine Word Problems
Finite String Recognizer
S2, S5 with incomplete transitions
S2 = …01; If next input is 1, then string could be prefix of (01)1(00)
S4 handles just this case!
S5 = …10; If next input is 1, then string could be prefix of (10)1(0)
S2 handles just this case!
0
Reset
S0
[0]
1
S4
[0]
S1
[0]
0
...0
S2
[0]
...01
Final State Diagram
...1
1
1
1
0
1
...10
0
S5
[0]
0
1
...010
S3
[1]
0
...100
S6
[0]
0,1
8-43
Finite State Machine Word Problems
Finite String Recognizer
module string
state_diagram SREG
title '010/100 string recognizer state machine state S0: if X then
Josephine Engineer, Itty Bity Machines, Inc.' state S1: if X then
u1 device 'p22v10';
state S2: if X then
state S3: if X then
"Input Pins
state S4: if X then
state S5: if X then
clk, X, RESET
pin 1, 2, 3;
state S6: goto S6;
"Output Pins
test_vectors ([clk,
Q0, Q1, Q2, Z
pin 19, 20, 21, 22;
[0,1,.X.] -> [0];
[.C.,0,0] -> [0];
Q0, Q1, Q2, Z istype 'pos,reg';
[.C.,0,0] -> [0];
[.C.,0,1] -> [0];
"State registers
[.C.,0,0] -> [1];
SREG = [Q0, Q1, Q2, Z];
[.C.,0,1] -> [0];
S0 = [0,0,0,0]; " Reset state
[.C.,0,0] -> [1];
S1 = [0,0,1,0]; " strings of the form ...0
[.C.,0,1] -> [0];
S2 = [0,1,0,0]; " strings of the form ...01
[.C.,0,0] -> [1];
S3 = [0,1,1,1]; " strings of the form ...010
[.C.,0,0] -> [0];
S4 = [1,0,0,0]; " strings of the form ...1
[.C.,0,1] -> [0];
S5 = [1,0,1,0]; " strings of the form ...10
[.C.,0,0] -> [0];
S6 = [1,1,0,0]; " strings of the form ...100
end string;
equations
[Q0.ar, Q1.ar, Q2.ar, Z.ar] = RESET; "Reset to S0
Introduction
S4
S2
S4
S2
S4
S2
else
else
else
else
else
else
S1;
S1;
S3;
S6;
S5;
S6;
RESET, X]->[Z])
ABEL Description
8-44
Finite State Machine Word Problems
Finite String Recognizer
Review of Process:
Introduction
• Write down sample inputs and outputs to understand specification
• Write down sequences of states and transitions for the sequences
to be recognized
• Add missing transitions; reuse states as much as possible
• Verify I/O behavior of your state diagram to insure it functions
like the specification
8-45
Introduction
Finite State Machine Word Problems
Complex Counter
A sync. 3 bit counter has a mode control M. When M = 0, the counter
counts up in the binary sequence. When M = 1, the counter advances
through the Gray code sequence.
Binary: 000, 001, 010, 011, 100, 101, 110, 111
Gray: 000, 001, 011, 010, 110, 111, 101, 100
Valid I/O behavior:
Mode Input M
0
0
1
1
1
0
0
Current State
000
001
010
110
111
101
110
Next State (Z2 Z1 Z0)
001
010
110
111
101
110
111
8-46
Introduction
Finite State Machine Word Problems
Complex Counter
One state for each output combination
Add appropriate arcs for the mode control
S0
[000]
1
S0
Reset
S1
0
0
0
S2
[010]
1
S2
0
S3
[011]
1
S6
011
H.Z 1
H.Z 0
0
1
M
0
110
S4
H.Z 2
H.Z 1
100
H.Z 2
0
S7
S5
[101]
0
0
0
1
S7
[111]
111
M
0
S5
101
H.Z 2
H.Z 0
1
0
0
1
M
H.Z 2
H.Z 1
H.Z 0
S6
[110]
1
S3
1
S4
[100]
1
1
M
010
H.Z 1
M
0
1
001
H.Z 0
S1
[001]
1
000
M
1
8-47
Finite State Machine Word Problems
Complex Counter
Introduction
module counter
title 'combination binary/gray code upcounter
Josephine Engineer, Itty Bity Machines, Inc.'
u1 device 'p22v10';
state_diagram SREG
state S0: goto S1;
"Input Pins
state S1: if M then S3 else S2;
clk, M, RESET
pin 1, 2, 3;
state S2: if M then S6 else S3;
state S3: if M then S2 else S4;
"Output Pins
state S4: if M then S0 else S5;
Z0, Z1, Z2
pin 19, 20, 21;
state S5: if M then S4 else S6;
state S6: goto S7;
Z0, Z1, Z2
istype 'pos,reg';
state S7: if M then S5 else S0;
"State registers
SREG = [Z0, Z1, Z2];
test_vectors ([clk, RESET, M] -> [Z0, Z1, Z2])
S0 = [0,0,0];
[0,1,.X.] -> [0,0,0];
S1 = [0,0,1];
[.C.,0,0] -> [0,0,1];
S2 = [0,1,0];
[.C.,0,0] -> [0,1,0];
S3 = [0,1,1];
[.C.,0,1] -> [1,1,0];
S4 = [1,0,0];
[.C.,0,1] -> [1,1,1];
S5 = [1,0,1];
[.C.,0,1] -> [1,0,1];
S6 = [1,1,0];
[.C.,0,0] -> [1,1,0];
S7 = [1,1,1];
[.C.,0,0] -> [1,1,1];
end counter;
equations
[Z0.ar, Z1.ar, Z2.ar] = RESET; "Reset to state S0
ABEL Description
8-48
Finite State Machine Word Problems
Traffic Light Controller
Introduction
A busy highway is intersected by a little used farmroad. Detectors
C sense the presence of cars waiting on the farmroad. With no car
on farmroad, light remain green in highway direction. If vehicle on
farmroad, highway lights go from Green to Yellow to Red, allowing
the farmroad lights to become green. These stay green only as long
as a farmroad car is detected but never longer than a set interval.
When these are met, farm lights transition from Green to Yellow to
Red, allowing highway to return to green. Even if farmroad vehicles
are waiting, highway gets at least a set interval as green.
Assume you have an interval timer that generates a short time pulse
(TS) and a long time pulse (TL) in response to a set (ST) signal. TS
is to be used for timing yellow lights and TL for green lights.
8-49
Introduction
Finite State Machine Word Problems
Traffic Light Controller
Picture of Highway/Farmroad Intersection:
Farmroad
C
HL
FL
Highway
Highway
HL
FL
C
Farmroad
8-50
Finite State Machine Word Problems
Traffic Light Controller
Introduction
• Tabulation of Inputs and Outputs:
Input Signal
reset
C
TS
TL
Description
place FSM in initial state
detect vehicle on farmroad
short time interval expired
long time interval expired
Output Signal
HG, HY, HR
FG, FY, FR
ST
Description
assert green/yellow/red highway lights
assert green/yellow/red farmroad lights
start timing a short or long interval
• Tabulation of Unique States: Some light configuration imply others
State
S0
S1
S2
S3
Description
Highway green (farmroad red)
Highway yellow (farmroad red)
Farmroad green (highway red)
Farmroad yellow (highway red)
8-51
Introduction
Finite State Machine Word Problems
Traffic Light Controller
Refinement of ASM Chart:
Start with basic sequencing and outputs:
S0
H.HG
H.FR
S1
H.HY
H.FR
S3
H.HR
H.FY
S2
H.HR
H.FG
8-52
Introduction
Finite State Machine Word Problems
Traffic Light Controller
Determine Exit Conditions for S0:
Car waiting and Long Time Interval Expired- C • TL
S0
S0
H.HG
H.FR
0
H.HG
H.FR
0
TL
TL • C
1
0
C
1
H.ST
1
H.ST
S1
H.HY
H.FR
S1
H.HY
H.FR
Equivalent ASM Chart Fragments
8-53
Finite State Machine Word Problems
Traffic Light Controller
S1 to S2 Transition:
Set ST on exit from S0
Stay in S1 until TS asserted
Similar situation for S3 to S4 transition
S1
H.HY
H.FR
0
TS
H.ST
Introduction
S2
H.HR
H.FG
1
8-54
Introduction
Finite State Machine Word Problems
Traffic Light Controller
S2 Exit Condition: no car waiting OR long time interval expired
S0
H.HG
H.FR
0
H.ST
1
TL • C
S3
H.HR
H.FY
TS
0
1
H.ST
S1
H.HY
H.FR
0
TS
H.ST
H.ST
1
S2
H.HR
H.FG
0
TL + C
1
Complete ASM Chart for Traffic Light Controller
8-55
Introduction
Finite State Machine Word Problems
Traffic Light Controller
Compare with state diagram:
TL + C
Reset
S0: HG
S0
TL•C/ST
S1: HY
TS/ST
TS
S1
S2: FG
S3
TS
TS/ST
S3: FY
TL + C/ST
S2
TL • C
Advantages of State Charts:
• Concentrates on paths and conditions for exiting a state
• Exit conditions built up incrementally, later combined into
single Boolean condition for exit
• Easier to understand the design as an algorithm
8-56
Finite State Machine Word Problems
Traffic Light Controller
module traffic
title 'traffic light FSM'
u1 device 'p22v10';
"Input Pins
clk, C, RESET, TS, TL
pin
1, 2,
3, 4,
"Output Pins
Q0, Q1, HG, HY, HR,
FG, FY, FR, ST
pin 14, 15, 16, 17, 18,
19, 20, 21, 22;
5;
HY
HR
FG
FY
FR
=
=
=
=
=
Introduction
!Q0 & Q1;
(Q0 & !Q1) # (Q0 & Q1);
Q0 & !Q1;
Q0 & Q1;
(!Q0 & !Q1) # (!Q0 & Q1);
state_diagram SREG
state S0: if (TL & C) then S1 with ST = 1
else S0 with ST = 0
state S1: if TS then S2 with ST = 1
else S1 with ST = 0
state S2: if (TL # !C) then S3 with ST = 1
else S2 with ST = 0
state S3: if TS then S0 with ST = 1
else S3 with ST = 0
Q0, Q1 istype 'pos,reg';
ST, HG, HY, HR,
FG, FY, FR istype 'pos,com';test_vectors
([clk,RESET, C, TS, TL]->[SREG,HG,HY,HR,FG,FY,FR,ST])
"State registers
[.X.,
1,.X.,.X.,.X.]->[ S0, 1, 0, 0, 0, 0, 1, 0];
SREG = [Q0, Q1];
[.C.,
0, 0, 0, 0]->[ S0, 1, 0, 0, 0, 0, 1, 0];
S0 = [ 0, 0];
[.C.,
0, 1, 0, 1]->[ S1, 0, 1, 0, 0, 0, 1, 0];
S1 = [ 0, 1];
[.C.,
0, 1, 0, 0]->[ S1, 0, 1, 0, 0, 0, 1, 0];
S2 = [ 1, 0];
[.C.,
0, 1, 1, 0]->[ S2, 0, 0, 1, 1, 0, 0, 0];
S3 = [ 1, 1];
[.C.,
0, 1, 0, 0]->[ S2, 0, 0, 1, 1, 0, 0, 0];
[.C.,
0, 1, 0, 1]->[ S3, 0, 0, 1, 0, 1, 0, 0];
equations
[.C.,
0, 1, 1, 0]->[ S0, 1, 0, 0, 0, 0, 1, 0];
[Q0.ar, Q1.ar] = RESET;
end traffic;
HG = !Q0 & !Q1;
ABEL Description
8-57
Finite State Machine Word Problems
Digital Combination Lock
Introduction
"3 bit serial lock controls entry to locked room. Inputs are RESET,
ENTER, 2 position switch for bit of key data. Locks generates an
UNLOCK signal when key matches internal combination. ERROR
light illuminated if key does not match combination. Sequence is:
(1) Press RESET, (2) enter key bit, (3) Press ENTER, (4) repeat (2) &
(3) two more times."
Problem specification is incomplete:
• how do you set the internal combination?
• exactly when is the ERROR light asserted?
Make reasonable assumptions:
• hardwired into next state logic vs. stored in internal register
• assert as soon as error is detected vs. wait until full combination
has been entered
Our design: registered combination plus error after full combination
8-58
Introduction
Finite State Machine Word Problems
Digital Combination Lock
Understanding the problem: draw a block diagram …
RESET
Operator Data
ENT ER
UNLOCK
KEY-IN
Combi nation
Loc k FSM ERROR
Internal
Combination
L0
L1
L2
Inputs:
Reset
Enter
Key-In
L0, L1, L2
Outputs:
Unlock
Error
8-59
Introduction
Finite State Machine Word Problems
Digital Combination Lock
Enumeration of states:
what sequences lead to opening the door?
error conditions on a second pass …
START state plus three key COMParison states
START
START entered on RESET
Exit START when ENTER is pressed
1
Res et
0
Enter
COMP0
0
1
KI = L0
N
Continue on if Key-In matches L0
Y
8-60
Introduction
Finite State Machine Word Problems
Digital Combination Lock
COMP0
IDLE1
Path to unlock:
KI = L 0
N
Y
Enter
1
COMP2
IDLE0
0
Wait for
Enter Key press
Enter
COMP1
0
KI = L2
N
Y
1
DONE
H.Unlock
Compare Key-IN
KI = L1
Y
N
Res et
0
1
START
8-61
Introduction
Finite State Machine Word Problems
Digital Combination Lock
Now consider error paths
Should follow a similar sequence as UNLOCK path, except
asserting ERROR at the end:
IDLE0'
ERROR3
IDLE1'
H.Error
Enter
ERROR1
1
0
Enter
ERROR2
0
Res et
0
1
1
START
COMP0 error exits to IDLE0'
COMP1 error exits to IDLE1'
COMP2 error exits to ERROR3
8-62
Introduction
Finite State Machine Word Problems
Digital Combination Lock
Reset + Enter
Reset
Start
Reset • Enter
Comp0
KI ° L0
KI = L0
Enter
Enter
Idle0
Idle0'
Enter
Equivalent State Diagram
Enter
Comp1
KI = L1
Error1
KI ° L1
Enter
Enter
Idle1
Idle1'
Enter
Enter
Comp2
KI = L2
Reset
Done
[Unlock]
Reset
Start
Error2
KI ° L2
Error3
[Error]
Reset
Reset
Start
8-63
Finite State Machine Word Problems
Combination Lock
Introduction
module lock
title 'comb. lock FSM'
u1 device 'p22v10';
equations
[Q0.ar, Q1.ar, Q2.ar, Q3.ar] = RESET;
UNLOCK = !Q0 & Q1 & Q2 & !Q3;"asserted in DONE
"Input Pins
ERROR = Q0 & !Q1 & Q2 & Q3; "asserted in ERROR3
clk, RESET, ENTER, L0, L1, L2, KI
pin
1, 2, 3, 4, 5, 6, 7;
state_diagram SREG
state START: if (RESET # !ENTER)
"Output Pins
then START else COMP0;
Q0, Q1, Q2, Q3, UNLOCK, ERROR
state COMP0: if (KI == L0) then IDLE0 else IDLE0p;
pin 16, 17, 18, 19, 14, 15;
state IDLE0: if (!ENTER) then IDLE0 else COMP1;
state COMP1: if (KI == L1) then IDLE1 else IDLE1p;
Q0, Q1, Q2, Q3 istype 'pos,reg';state IDLE1: if (!ENTER) then IDLE1 else COMP2;
UNLOCK, ERROR istype 'pos,com';state COMP2: if (KI == L2) then DONE else ERROR3;
state DONE: if (!RESET) then DONE else START;
"State registers
state IDLE0p:if (!ENTER) then IDLE0p else ERROR1;
SREG
= [Q0, Q1, Q2, Q3];
state ERROR1:goto IDLE1p;
START
= [ 0, 0, 0, 0];
state IDLE1p:if (!ENTER) then IDLE1p else ERROR2;
COMP0
= [ 0, 0, 0, 1];
state ERROR2:goto ERROR3;
IDLE0 = [ 0, 0, 1, 0];
state ERROR3:if (!RESET) then ERROR3 else START;
COMP1 = [ 0, 0, 1, 1];
IDLE1 = [ 0, 1, 0, 0];
test_vectors
COMP2 = [ 0, 1, 0, 1];
DONE = [ 0, 1, 1, 0];
end lock;
IDLE0p = [ 0, 1, 1, 1];
ERROR1 = [ 1, 0, 0, 0];
IDLE1p = [ 1, 0, 0, 1];
ERROR2 = [ 1, 0, 1, 0];
ERROR3 = [ 1, 0, 1, 1];
8-64
Finite State Machine Word Problems
Design Steps
Introduction
1. Understand the problem
2. Make reasonable assumptions when specifications are not complete
3. Start by deriving the states and state transitions that lead to the goal
of FSM
4. Consider the error conditions and the transitions that lead to error
states
8-65
Chapter Review
Introduction
Basic Timing Behavior an FSM
• when are inputs sampled, next state/outputs transition and stabilize
• Moore and Mealy (Async and Sync) machine organizations
outputs = F(state) vs. outputs = F(state, inputs)
First Two Steps of the Six Step Procedure for FSM Design
• understanding the problem
• abstract representation of the FSM
Abstract Representations of an FSM
• ASM Charts, Hardware Description Languages
Word Problems
• understand I/O behavior; draw diagrams
• enumerate states for the "goal"; expand with error conditions
• reuse states whenever possible
8-66