Transcript The Verilog Hardware Description Language

332:437 Lecture 8
Verilog and Finite State Machines
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Finite State Machines
Discrete Time Simulation
Gate Level Modeling
Delays
Summary
Material from The Verilog Hardware Description Language,
By Thomas and Moorby, Kluwer Academic Publishers
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Lecture 8
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Finite State Machines — Review
 In the abstract, an FSM can be defined by:
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A set of states or actions that the system will perform
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The inputs to the FSM that will cause a sequence to occur
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The outputs that the states (and possibly, the inputs) produce
 There are also two special inputs
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A clock event, sometimes called the sequencing event, that causes the
FSM to go from one state to the next
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A reset event, that causes the FSM to go to a known state
outputs
inputs
FSM
clock
reset
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FSM Review
 The traditional FSM diagram
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We looked at State Transition Diagrams (and Tables) last time
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… and ended up with a diagram that looked like this
We’ll talk
about how to
design this
inputs
clock
reset
outputs
Combinational
Logic
Current State
Register
next
state
We’ll talk
about what
these are
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Verilog for the D Flip-Flop
Current Next state, after
state (now) clock event
Q+
D Q
0
0 0
0
0 1
1
1 0
1
1 1
Note that it doesn’t matter
what the current state (Q)
is. The new state after the
clock event will be the value
on the D input.
module DFF
(output reg q,
input
d, clk, reset);
always
@(posedge clk or negedge reset)
if (~reset)
q <= 0;
else q <= d;
endmodule
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The change in q is
synchronized to the
clk input.
The reset is an
asynchronous reset
(q doesn’t wait for
the clk to change).
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Clock Events on Other Planets
 Trigger alternatives
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For flip flops, the clock event can either be a positive or negative
edge
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Both have same next-state table
D
Q
C
clk
Current
Next state, after
state, now clock event
Positive edge triggered
Flip Flop
D
clk
D
0
0
1
1
Q
Q
0
1
0
1
Q+
0
0
1
1
C
Negative edge triggered Flip
Flop (bubble indicates
negative edge)
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Moore Machine — 111 Detector
Q2
D1
Q1
Z
reset
X
Q1
D2
Q2
Q2’
reset
clock
reset
 Note how the reset is connected
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Reset will make both of the FFs zero, thus putting them into state A.
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Most FFs have both reset and “preset’’ inputs (preset sets the FF to one).

The reset connections (to FF reset and preset) are determined by the state
assignment of the reset state.
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Verilog Organization for FSM
Q2
D1
Q1
Z
reset
X
Q1
D2
Q2
Q2’
reset
clock
reset
 Two always blocks
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One for the combinational logic — next state and output logic
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One for the state register
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Verilog Behavioral Specification
module FSM (x, z, clk, reset);
input
clk, reset, x;
output
z;
reg
[1:2] q, d;
reg
z;
always
@(posedge clk or negedge reset)
if (~reset)
q <= 0;
else q <= d;
 Things to note
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reg [1:2] — matches
numbering in state
assignment (Q2 is least
significant bit in counting)
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<= vs. =
always @(x or q)
begin
d[1] = q[1] & x | q[2] & x;
d[2] = q[1] & x | ~q[2] & x;
z = q[1] & q[2];
end
The sequential part
(the D flip flop)
The combinational
logic part
next state
output
endmodule
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Processes Without Sensitivity List or
wait Statement
 Run forever – example:
always
begin
x <= a and b and c;
end
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Synopsys Deletes All Useless Hardware
from Your Design
 Synthesis: Since x can never be other than 0, hardwire x to 0
 Moral:
1.
Signals are not updated until end of process even if they
change in the middle of it due to <= operator
2.
Expressions based on current value of signals on RHS of
<= symbol
3.
Signals updated with value in last assignment statement
in process
4.
Order of concurrent signal assignment statements is of
no consequence
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Benefit of Don’t Cares
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Don’t care condition produces less hardware
s1
0
1
• y <= s1 + s0
s0
• Rather than
• y <= s1 s0 + s1 s0
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0
1
x
1
0
1
s1
0
1
0
1
0
1
0
1
s0
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Verilog Overview
 Verilog is a concurrent language
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Aimed at modeling hardware — optimized for it!
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Typical of hardware description languages (HDLs), it:
 Controls time
 Provides for the specification of concurrent activities
 Stands on its head to make the activities look like they happened at
the same time — Why?
 Allows for intricate timing specifications — Why?
 A concurrent language allows for:
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Multiple concurrent “elements”
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An event in one element to cause activity in another. (An event is
an output or state change at a given time)
 Based on interconnection of the element’s ports
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Logical concurrency — software
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True physical concurrency — e.g., “<=” in Verilog
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Discrete Time Simulation
 Discrete Time Simulation
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Models evaluated and state updated only at time intervals — n
 Even if there is no change on an input
 Even if there is no state to be changed
 Need to execute at finest time granularity
 Might think of this as cycle accurate — things only happen
@(posedge clock)
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You could do logic circuits this way, but either:
 Lots of gate detail lost — as with cycle accurate above (no gates!)
 Lots of simulation where nothing happens — every gate is executed
whether an input changes or not.
 Discrete Event Simulation…
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Picks up simulation efficiency due to its selective evaluation
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Only execute models when inputs change
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Discrete Event (DE) Simulation
 Discrete Event Simulation
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Events — changes in state at discrete times. These cause other
events to occur
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Only execute something when an event has occurred at its input
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Events are maintained in time order
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Time advances in discrete steps when all events for a given time
have been processed
 Quick example
B
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Gate A changes its output.
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Only then will B and C execute
A
C
 Observations
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The elements in the diagram don’t need to be logic gates
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DE simulation works because there is a sparseness to gate
execution — maybe only 12% of gates change at any one time.
 The overhead of the event list pays off then.
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Observations
 Hmm…
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Implicit model execution of fanout elements
B
 Implicit?
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Concurrency — is it guaranteed? How?
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Time — a fundamental thingie
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Can’t you represent this all in C? After all,
the simulator is written in it!
A
C
 Or assembly language?
 What’s the issue?
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Or how about Java? Ya-know, aren’t objects
like things you instantiate just like in
Verilog?
 Can’t A call the port-2 update method on
object B to make a change?
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A Gate Level Model
 A Verilog description of an SR latch
A module
is defined
name of the
module
Draw the circuit
module nandLatch
(output
q, qBar,
input
set, reset);
The module has ports
that are typed
type and delay of
primitive gates
nand #2
g1 (q, qBar, set),
g2 (qBar, q, reset);
endmodule
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primitive gates with
names and
interconnections
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A Gate Level Model
 Things to note:
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It doesn’t appear “executable” — no for loops, if-then-else, etc.
 It’s not in a programming language sense, rather it describes the
interconnection of elements
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A new module made up of other modules (gates) has been defined
 Software engineering aspect — we can hide detail
module nandLatch
(output
q, qBar,
input
set, rese)t;
nand #2
g1 (q, qBar, set),
g2 (qBar, q, reset);
endmodule
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Kinds of Delays
 Transport delay
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Input to output delay (sometimes
“propagation”)
 Zero delay models (all transport delays = 0)
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Functional testing
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There’s no delay, not cool for circuits with
feedback!
a
b
c
 — transport delay
 Unit delay models (all transport delays = 1)
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All gates have delay 1. OK for feedback
 Edge sensitive — delay is value sensitive
nand #(3, 4, 5) (c, a, b);
rising delay
delay to z
falling delay
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Some More Gate Level Examples
 An adder
instance names
and delays
optional
module adder
(output
carryOut, sum,
input
aInput, bInput, carryIn);
sum
xor
(sum, aInput, bInput, carryIn);
or
(carryOut, ab, bc, ac);
and
(ab, aInput, bInput),
ab
carryOut
bc
(bc, bInput, carryIn),
ac
(ac, aInput, carryIn);
endmodule
list of gate instances
of same function
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aInput
implicit wire
declarations
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carryIn
bInput
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Adder With Delays
 An adder with delays
module adder
(output
carryOut, sum,
input
aInput, bInput, carryIn);
xor
#(3, 5)
(sum, aInput, bInput, carryIn);
or
#2
(carryOut, ab, bc, ac);
and
#(3, 2)
(ab, aInput, bInput),
(bc, bInput, carryIn),
(ac, aInput, carryIn);
endmodule
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each AND gate
instance has the
same delay
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Adder, Continuous Assign
 Using “continuous assignment”
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Continuous assignment allows you to specify combinational
logic in equation form
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Anytime an input (value on the right-hand side) changes, the
simulator re-evaluates the output
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No gate structure is implied — logic synthesis can design it.
 The description is more abstract
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A behavioral function may be called — details later
module adder
(output
carryOut, sum,
input
aInput, bInput, carryIn);
assign
sum = aInput ^ bInput ^ carryIn,
carryOut = (aInput & bInput) | (bInput & carryIn) |
(aInput & carryIn);
endmodule
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I’m Sick of This Adder
 Continuous assignment assigns continuously
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Delays can be specified (same format as for gates) on whole
equation
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No instances names — nothing is being instantiated.
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Given the same delays in this and the gate-level model of an adder,
there is no functional difference between the models
 FYI, the gate-level model gives names to gate instances, allowing back
annotation of times.
module adder
(output
carryOut, sum,
input
aInput, bInput, carryIn);
assign
#(3, 5)
sum = aInput ^ bInput ^ carryIn;
assign
#(4, 8)
carryOut = (aInput & bInput) | (bInput & carryIn) |
(aInput & carryIn);
endmodule
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Summary
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Finite State Machines
Discrete Time Simulation
Gate Level Modeling
Delays
Summary
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