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Unit 3 Finite State Machine

If we hear, we forget; if we see, we remember; if we do, we understand.

Department of Communication Engineering, NCTU -- Proverb

3.1 Derivation of State Graphs and Tables

Department of Communication Engineering, NCTU

Hardware Project Unit 3 Finite State Machine Sau-Hsuan Wu

 A Finite State Machine (FSM) is simply a state register that holds the current state and some combinational logic which calculates the next state and outputs based on the current state and the inputs  FSM types  Moore machine : the outputs are functions of the present state only  Mealy machine : the outputs are functions of both the present state and the inputs

Department of Communication Engineering, NCTU

Hardware Project

 A Moore FSM  MTS turnstile

Unit 3 Finite State Machine Initialization Easy Cards Passing Locked Sau-Hsuan Wu Unlocked Passing Violation (Unlocked) Alarm Reset Department of Communication Engineering, NCTU

Hardware Project Unit 3 Finite State Machine Sau-Hsuan Wu

 State diagram representation    Locked ST: S 0 , Unlocked ST : S 1 and Violation ST: S 2 Inputs    Presence of Easy Card  Passenger passing  u 1 u 0 =1, otherwise u =1, otherwise u 1 =0 0 Alarm reset  u 2 =1, otherwise u 2 =0 Outputs (Z) =0

u 0 =0 XNOR u 1 =0

   S 0 S 1 S 2  Locked  Unlocked  Unlocked

u 1 =1 S 0 u 0 =1 u 2 =1 u 1 =1 S 2 S 1 u 1 =0 u 2 =0 Department of Communication Engineering, NCTU

Hardware Project Unit 3 Finite State Machine Sau-Hsuan Wu

 State transition table S

S 0 S 1 S 2

S + u 2 u 1 u 0 = 000 001 010 011 100 101 110 111

S 0 S 1 S 2 S 0 S 0 S 0 S 0 S 0 S 1 S 2

− −

S 0 S 2 S 1

− − − −

S 0 S 0 S 0 u 0 =0 XNOR u 1 =0

−

S 0 S 0 u 1 =1 u 0 =1

Z 1 0 0

u 2 =1 u 1 =1 S 2 S 1 u 2 =0 u 1 =0 Department of Communication Engineering, NCTU

Hardware Project Unit 3 Finite State Machine Sau-Hsuan Wu

 Binary state assignment S

S 0 S 1 S 2

S + u 2 u 1 u 0 = 000 001 010 011 100 101 110 111

S 0 S 1 S 2 S 0 S 0 S 0 S 0 S 0 S 1 S 2

− −

S 0 S 2 S 1

− −

S 0

−

S 0

−

S 0

−

S 0

S Q 1 Q 0

00 01 10 11

Q 1 + Q 0 + u 2 u 1 u 0 = 000 001 010 011 100 101 110 111

00 01 10 00 00 00 00 00 01 10

− − − −

00 10

−

− − −

− −

− Z 1 0 0 − 1 0 0 Z

Department of Communication Engineering, NCTU

Hardware Project Unit 3 Finite State Machine Sau-Hsuan Wu

 Next-State maps Q 1 Q 0 u 2 u 1 u 0 = 000 001 010 011 100 101 110 111

00 00 01 10 00 00 00 00 00 01 10 11 u 2 1/0 Q 1 Q 0 u 1 u 0

0 X

X 0

0 1

01 10

− 0

0 X X 0

0 X 0 X 0 X X X

Q 1 +

0 X X 0 − − − 0

1 X X 0 X

00 10

−

− − − − −

− −

Q 1 Q 0 u 1 u 0

0 X

− X 0

u 2 1/0

X X X

X X

− X X 0

0 1 X

− X X 0

0 0 X 1

0 0 0 X

Q 0 +

0 X 0 0

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Z 1 0 0 − 8

Hardware Project Unit 3 Finite State Machine Sau-Hsuan Wu

 Characteristic equations

u 2 1/0 Q 1 Q u 1 u 0 0

00 00

0 X

X 0

0 1 0

0 X X 0

0 X 0 X 0 X X 0 X

Q 1 +

X X 0

1 X 0 X X 0 1  Q 1 + = Q 1 u 2 ’ + Q 0 ’ u 2 ’ u 1 u 0 ’

Q 1 Q u 1 u 0 0

00 00

0 X

01 u 2 1/0 11

X 1 X

0 0 0

1 X X 0

0 X 1 X 0 X X 0 X

Q 0 +

X X 0

0 X 0 X X 0 0 Q 0 + = Q 0 u 1 ’ + Q 0 u 0 + u 2 ’ u 1 ’ u 0

Department of Communication Engineering, NCTU

Hardware Project Unit 3 Finite State Machine Sau-Hsuan Wu

 Output equations Q 1 Q 0

00 01 10 11

u 2 u 1 u 0 = 000 001 010 011 100 101 110 111

00 01 10 00 00 00 00 00 01 10

− − − −

00 10

−

− − −

− −

− Z 1 0 0 −/ (1)   Characteristic equations: Q 1 + = Q 1 u 2 ’ + Q 0 ’ u 2 ’ u 1 u 0 ’ Output equation : Z = Q 1  Q 0 (or = (Q 1 || Q 0 ) ’ Q 0 + = Q 0 u 1 ’ + Q 0 u 0 + u 2 ’ u 1 ’ u 0

Department of Communication Engineering, NCTU

Hardware Project Unit 3 Finite State Machine Sau-Hsuan Wu

 Circuit realization with D-FFs   Characteristic equations: Q 1 + = Q 1 u 2 ’ + Q 0 ’ u 2 ’ u 1 u 0 ’ Output equation : Z = Q 1  Q 0 Q 0 + = Q 0 u 1 ’ + Q 0 u 0 + u 2 ’ u 1 ’ u 0

u 2 u 1 u 0 Q 1 +

D Q CK CLR

Q 1 Z u 1 u 0 u 2 Q 0 +

D Q CK CLR

Q 0 CLK Department of Communication Engineering, NCTU

Hardware Project Unit 3 Finite State Machine Sau-Hsuan Wu

 Another Moore FSM  An elevator controller (Up, Down, Open and Timer start) req > floor u,d,o, t = 1,0,0,0 GoingUp !(req > floor) u,d,o,t = 0,0,1,0 req > floor Idle req == floor !(timer < 10) req < floor u,d,o,t = 0,1,0,0 GoingDn DoorOpen !(req

Department of Communication Engineering, NCTU

Hardware Project Unit 3 Finite State Machine

 The general model of a Moore machine

X 1 X 2 X m Q 1 + Com.

Logic Q 2 + Q m +

D Q

Q 1

CK CLR D Q

Q 2

CK CLR D Q CK CLR

Q m Com.

Logic Sau-Hsuan Wu Z 1 Z 2 Z m Department of Communication Engineering, NCTU

Hardware Project Unit 3 Finite State Machine

 A Mealy FSM  A traffic light controller

Farmroad C HL FL Sau-Hsuan Wu Highway Highway HL C Farmroad FL Department of Communication Engineering, NCTU

Hardware Project Unit 3 Finite State Machine Sau-Hsuan Wu

 Tabulation of inputs and outputs

Input Signal

Reset C TS TL

Description

place FSM in initial state detect vehicle on farmroad short time interval expired long time interval expired



Output Signal

HG, HY, HR FG, FY, FR ST

Description

assert green/yellow/red highway lights assert green/yellow/red farmroad lights start timing a short or long interval

Tabulation of unique states

State

S 0 S 1 S 2 S 3

Description

Highway green (farmroad red) Highway yellow (farmroad red) Farmroad green (highway red) Farmroad yellow (highway red) Department of Communication Engineering, NCTU

Hardware Project Unit 3 Finite State Machine

 The state diagram

S 0 : HG (FR) S 1 : HY (FR) S 2 : FG (HR) S 3 : FY (HR) Reset TL

C /ST S 0 TL ’ + C ’ TS/ST Sau-Hsuan Wu TS ’ S 1 S 3 TS ’ TS/ST S 2 TL ’ + C TL

C ’ /ST Department of Communication Engineering, NCTU

Hardware Project Unit 3 Finite State Machine Sau-Hsuan Wu

 State transition table

Reset T L ’ + C ’ S 0 S 1 S 2 S 3 HG = S 0 FR = S 0 + S 1 HY = S 1 FG = S 2 HR = S 2 + S 3 FY = S 3 S T = ?

T L

C /S T T S ’ T S /S T S 1 S 0 T S /S T S 3 S 2 T L

C ’ /S T T L ’ + C

S +

S T CT L T S =000 001 010 011 100 101 110 111

S 0 |S T ’ S 1 |S T ’ S 2 |S T ’ S 3 |S T ’ S 0 |S T ’ S 2 |S T S 2 |S T ’ S 0 |S T S 0 |S T ’ S 1 |S T ’ S 3 |S T S 3 |S T ’ S 0 |S T ’ S 2 |S T S 3 |S T S 0 |S T S 0 |S T ’ S 1 |S T ’ S 2 |S T ’ S 3 |S T ’ S 0 |S T ’ S 2 |S T S 2 |S T ’ S 0 |S T S 1 |S T S 1 |S T ’ S 2 |S T ’ S 3 |S T ’ S 1 |S T S 2 |S T S 2 |S T ’ S 0 |S T T S ’ Department of Communication Engineering, NCTU

Hardware Project

S 0 S 1 S 2 S 3 Unit 3 Finite State Machine Sau-Hsuan Wu

S +

S T CT L T S =000 001 010 011 100 101 110 111

S S 0 2 |S |S T S 1 |S T ’ T S 3 |S T ’ ’ ’ S 0 |S T ’ S S 2 |S T ’ S 2 0 |S |S T T S S S S 0 1 3 3 |S |S |S |S T T T T ’ ’ ’ S 0 |S T ’ S S S 2 3 0 |S |S |S T T T S S S S 0 1 2 3 |S |S |S |S T T T T ’ ’ ’ ’ S 0 |S T ’ S S S 2 2 0 |S |S |S T T T ’ S S S S 1 2 3 1 |S |S |S |S T T T T ’ ’ ’ S S S S 2 1 2 0 |S |S |S |S T T T T ’

00 01 11 10

S +

S T CT L T S =000 001 010 011 100 101 110 111

00 |0 00 |0 00 |0 00 |0 00 |0 00 |0 01 |1 01 |1 01|0 11 |1 01 |0 11 |1 01 |0 11 |1 01 |0 11 |1 11 |0 10 |0 11 |0 00|1 10|1 10 |0 10|1 00|1 11 |0 10 |0 11 |0 00|1 11 |0 10 |0 11|0 00|1 Department of Communication Engineering, NCTU

Hardware Project Unit 3 Finite State Machine Sau-Hsuan Wu

S S +

S T CT L T S =000 001 010 011 100 101 110 111

00 |0 00 |0 00 |0 00 |0 00 |0 00 |0 01 |1 01 |1 00 01 11 01|0 11 |0 11 |1 11 |0 01 |0 10|1 11 |1 10|1 01 |0 11 |0 11 |1 11 |0 01 |0 11 |0 10 |0 10 10 |0 00|1 10 |0 00|1 10 |0 00|1 C 1/0 Q 1 Q 0

T L T S 0

0 0

1 0

1 1 0

0 1 1 1 0 1 1 0

Q 1 +

0 0

0 1 1 1 0 0

0 0 0 1 1 1 1

Q 1 Q 0

T L T S 0

0 1

C 1/0

1 0

0 0

0 1 1 1 0 1 1 0

Q 0 +

0 1

0 1 1 0 0

Department of Communication Engineering, NCTU

0 1 1 1 0 0 0

11 |1 11|0 00|1

Hardware Project Unit 3 Finite State Machine Sau-Hsuan Wu

S S +

S T CT L T S =000 001 010 011 100 101 110 111

00 |0 00 |0 00 |0 00 |0 00 |0 00 |0 01 |1 01 |1 00 01 11 10 01|0 11 |0 10 |0 11 |1 11 |0 00|1 01 |0 10|1 10 |0 11 |1 10|1 00|1 01 |0 11 |0 10 |0 11 |1 11 |0 00|1 01 |0 11 |0 10 |0 C 1/0 Q 1 Q 0

T L T S 0

0 0

0 0 0

0 1 1 0 1 0 0 1

S T

1 1

0 1 1 1 1 1

0 0 0 0 1 0 0

HG = S 0 FR = S 0 + S 1 HY = S 1 FG = S 2 HR = S 2 + S 3 FY = S 3 S T =

Q 1 Q 0

’

T S + Q 1

’

Q 0 T S + Q 1

’

Q 0

’ C

T L + Q 1 Q 0

C’

T L

Department of Communication Engineering, NCTU 11 |1 11|0 00|1

Hardware Project Unit 3 Finite State Machine

 The general model of a Mealy machine

X 1 X 2 Z 1 Z 2 X m Q 1 + Com.

Logic Q 2 + Q m + Z m

D Q CK CLR

Q 1

D Q CK CLR

Q 2

D Q CK CLR

Q m Sau-Hsuan Wu Department of Communication Engineering, NCTU

Hardware Project Unit 3 Finite State Machine S T

 Circuit realization using a Mealy machine

Plant Reset

D Q CK CLR D Q CK CLR

T L

C /S T CLK T S ’ S 1 CntPre VDD Counter for T S

DN D CK Pre

T S T S /S T Counter for T L

DN D CK Pre

T L Sau-Hsuan Wu S 0 T L ’ + C ’ T S /S T T S ’ S 3 S 2 T L

C ’ /S T T L ’ + C FSM Department of Communication Engineering, NCTU

Hardware Project Unit 3 Finite State Machine

 Timing diagram using a Mealy machine

CLK Q 1 Q 0 T L T S S 0 S 1 S 2 C HG = S0 S T CntPre S T =

Q 1 Q 0

’

T S + Q 1

’

Q 0 T S + Q 1

’

Q 0

’ C

T L + Q 1 Q 0

C’

T L

Reset T L

C /S T T S ’ T S /S T S 1 Department of Communication Engineering, NCTU Sau-Hsuan Wu S 3 S 0 T L ’ + C ’ T S /S T S 3 S 2 T L

C ’ /S T T L ’ + C

Hardware Project Unit 3 Finite State Machine Sau-Hsuan Wu

 An alternative realization with a Moore machine

Plant S T CLK VDD Counter for T S

DN ENA D CK Pre

Counter for T L

DN ENA D CK Pre

T S T L T S ’ Reset T L

C S 1 S T S 0 S T ’ T L ’ + C ’ T S T S ’ ST S 3 S T T S S 2 S T ’ T L

C ’ T L ’ + C FSM S T =

Q 1 Q 0

’

+ Q 1

’

Q 0

Notice: need more states to generate the Pre signal if needed!! Department of Communication Engineering, NCTU

Hardware Project Unit 3 Finite State Machine

 Timing diagram using a Moore machine

CLK Q 1 Q 0 T L T S S 0 S 1 S 2 C HG = S0 S T S T =

Q 1 Q 0

’

+ Q 1

’

Q 0

T S ’ Reset T L

C S 1 S T T S Department of Communication Engineering, NCTU Sau-Hsuan Wu S 3 S 0 S T ’ ST T L ’ + C ’ T S 3 S T S T S ’ S 2 S T ’ T L

C ’ T L ’ + C

Hardware Project Unit 3 Finite State Machine

 The general model of a digital circuit

X 1 X 2 Z 1 Z 2 X P Z Q IN 1 CS 1 Plant IN 2 FSM CS 2 IN R CS M Sau-Hsuan Wu Department of Communication Engineering, NCTU

Hardware Project Unit 3 Finite State Machine Sau-Hsuan Wu

 Difference between a Moore machine and a Mealy machine    The outputs of a Moore FSM are synchronized with the CLK, however the outputs of a Mealy machine are not The disadvantages of Moore FSMs    In general, more states are required to generate outputs The action of the plant that the FSM controls is always one CLK period lagging behind the control signals The above two points are right the advantages of Mealy FSMs The disadvantages of Mealy FSMs   Outputs of FSMs must be sampled with FFs if synchronization is required Glitches and spikes

S T

D Q CK CLR D Q CK CLR

CntPre Department of Communication Engineering, NCTU

Hardware Project Unit 3 Finite State Machine Sau-Hsuan Wu

  Serial data code converter Design a code converter that convert an NRZ-coded bit stream to a Manchester-coded bit stream

Department of Communication Engineering, NCTU

Hardware Project Unit 3 Finite State Machine Sau-Hsuan Wu

   Realize the code converter with a Mealy machine Use a clock Clock2 which is twice the data rate The only two possible input sequences are 00 and 11 S

S 0 S 1 S 2

S + Z X= 0 X=1 X= 0 X=1

S 1 S 0

−

S 2

−

S 0

0 1 − 1 − 0

Reset 0 /0 S 1 Department of Communication Engineering, NCTU S 0 0/1 1/0 1/1 S 2

Hardware Project Unit 3 Finite State Machine Sau-Hsuan Wu

 The timing diagram using the Mealy machine

CLK2 NRZ 0 0 Manchester (ideal) S 0 1 S 1 0 Z (actual) 1 1 S 0 1 1 0 S 2 0 1 S 0 1 1 0 S 2 0 1 S 0 1 1 0 S 2 0 0 S 0 0 S 0 0 1 S 1 1 0 /0 1/1 S 1 Department of Communication Engineering, NCTU 0/1 1/0 S 2

Hardware Project Unit 3 Finite State Machine Sau-Hsuan Wu

 Redesign the data converter with a Moore machine

Department of Communication Engineering, NCTU

Hardware Project Unit 3 Finite State Machine Sau-Hsuan Wu

 The timing diagram using the Moore machine

Output is one clock lagging behind the input sequence Department of Communication Engineering, NCTU

3.2 Data Path and FSM

Department of Communication Engineering, NCTU

Hardware Project Unit 3 Finite State Machine

 The general model of a digital circuit

X 1 X 2 Z 1 Z 2 X P Z Q IN 1 CS 1 Plant IN 2 FSM CS 2 IN R CS M Sau-Hsuan Wu Department of Communication Engineering, NCTU

Hardware Project Unit 3 Finite State Machine

 A plant usually includes   A data path over which data are processed  A data path may include     An arithmetic and logic unit (ALU) Registers Counters Decoders Peripherals which may include  Input devices like key boards and mice  Storages devices like memories and disks  Output devices  Communications interface like USB, RS232, and Eithernet    Speaker Printer Displays like LCD and 7-segment displays

Department of Communication Engineering, NCTU Sau-Hsuan Wu

Hardware Project Unit 3 Finite State Machine Sau-Hsuan Wu

 Data path and FSM go hand in hand in digital design  A signal processing scheme is usually partitioned into a sequence of processing stages  Data path decides the number of stages the data is processed and the paths of data flow in between the stages  Data at the outputs of each stage are stores in registers  The complexity or in other words the levels of logics in each stage decides the processing speed   On the other hand the number of stages decides the processing delay FSM controls data’s movement in data path

Department of Communication Engineering, NCTU

Hardware Project Unit 3 Finite State Machine

 Data path for bubble sorting of 4 words

Sau-Hsuan Wu DIP SW Reg 0 CS0 Reg 1 A A B CS1 CS4 Reg 2 B CS2 CS5 S0 S1 S2 S3 Reg 3 CS3 Department of Communication Engineering, NCTU A > B A = B

Hardware Project Unit 3 Finite State Machine

 Draw a flow chart

Idle Load B St N Load Data Counter - Load Cnt3=0 Y Load A B>A Load LW Sau-Hsuan Wu Cnt1=0 Cnt 0 - N Cnt 0 = 2 Load HW Cnt0=0 N Cnt1=Cnt0 Cnt 1 - Department of Communication Engineering, NCTU

Hardware Project Unit 3 Finite State Machine

 Checking the Timing diagram

Sau-Hsuan Wu CLK Idle St Load Cnt 3 XX Cnt 0 Cnt 1 11 10 XX 01 XX 00 10 10 Department of Communication Engineering, NCTU

Hardware Project Unit 3 Finite State Machine Sau-Hsuan Wu

 Sequential machines are commonly partitioned into data path units and control units

Datapath Unit Datapath Logic Control inputs Clock FSM Control signals Datapath Registers

 The synthesis of a sequential machine usually includes:  Constructing the datapath units    Designing FSMs to control the data flow Realizing the control signals Checking the timing of signals

Department of Communication Engineering, NCTU

3.3 Algorithm State Machine

Department of Communication Engineering, NCTU

Hardware Project Unit 3 Finite State Machine Sau-Hsuan Wu

   Datapath units consist of:  Arithmetic units :    Arithmetic and logic units (ALU) Storage registers Logic for moving data :  through the system   between the computation units and internal registers to and from the external environments Control units are commonly modeled by  State transition graphs (STGs)  Algorithm state machine (ASM) charts for FSM A combined control-dataflow sequential machine is modeled by ASM and datapath (ASMD) charts

Department of Communication Engineering, NCTU

Hardware Project Unit 3 Finite State Machine Sau-Hsuan Wu

  Algorithm State Machine (ASM) Charts  State transition graphs only indicate the transitions that result from inputs  Not only does ASM display the state transitions, it also models the evolution of states under the application of input datas An ASM chart is formed with three fundamental elements

Department of Communication Engineering, NCTU

Hardware Project Unit 3 Finite State Machine Sau-Hsuan Wu

 Both Mealy and Moore machines can be represented by ASM  The outputs of a Moore machine are listed inside a state box  Conditional outputs (Mealy outputs) are placed in conditional output boxes

Start En C <= C+1 Department of Communication Engineering, NCTU

Hardware Project Unit 3 Finite State Machine Sau-Hsuan Wu

    A sequential machine is partitioned into a controller and a datapath, and the controller is described by an ASM The ASM chart can be modified to link to the datapath that is under control of the ASM The modified ASM is referred to as the algorithm state machine and datapath (ASMD) chart ASMD is different from ASM in that : each of the transition path of an ASM is annotated with the associated concurrent

register

operations of datapath

Department of Communication Engineering, NCTU

Hardware Project Unit 3 Finite State Machine

 An ASMD chart for a up-down counter

Sau-Hsuan Wu Up-down counter with asynchronous reset Up-down counter with synchronous reset Reset Count <= 0 Count <= Count - 1 Count <= 0 Start Count <= Count + 1 Start Clr Up Up Count <= Count + 1 Department of Communication Engineering, NCTU Count <= Count - 1

Hardware Project Unit 3 Finite State Machine Sau-Hsuan Wu

 ASM v.s. ASMD charts for a counter with enable

ASM chart representation ASMD chart representation Start En C <= C+1 Start En Enable DP Department of Communication Engineering, NCTU Count <= Count + 1

Hardware Project Unit 3 Finite State Machine

 A electronic dice game

Sau-Hsuan Wu Department of Communication Engineering, NCTU

Hardware Project Unit 3 Finite State Machine

 Flowchart for dice game

Sau-Hsuan Wu Department of Communication Engineering, NCTU

Hardware Project Unit 3 Finite State Machine

 Convert flowchart to state machine chart

Sau-Hsuan Wu Department of Communication Engineering, NCTU

Hardware Project Unit 3 Finite State Machine

 State machine chart

Sau-Hsuan Wu Department of Communication Engineering, NCTU

Hardware Project

 State graph

Unit 3 Finite State Machine Sau-Hsuan Wu Department of Communication Engineering, NCTU

Hardware Project

 Next-state map

Unit 3 Finite State Machine Sau-Hsuan Wu Department of Communication Engineering, NCTU

Hardware Project

 Realization

Unit 3 Finite State Machine Sau-Hsuan Wu Department of Communication Engineering, NCTU

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Transcript S 0

Unit 3 Finite State Machine

3.1 Derivation of State Graphs and Tables

3.2 Data Path and FSM

3.3 Algorithm State Machine

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