Transcript Introduction to basic concepts on asynchronous circuit design
Logic synthesis from concurrent specifications
Jordi Cortadella Universitat Politecnica de Catalunya Barcelona, Spain In collaboration with M. Kishinevsky, A. Kondratyev, L. Lavagno and A. Yakovlev 1
Outline Overview of the synthesis flow Specification State graph and next-state functions State encoding Implementability conditions Speed-independent circuit Complex gates C-element architecture Review of some advanced topics 2
Book and synthesis tool J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno and A. Yakovlev, Logic synthesis for asynchronous controllers and interfaces, Springer-Verlag, 2002 petrify: http://www.lsi.upc.es/petrify 3
Design flow Specification (STG) Reachability analysis State Graph State encoding SG with CSC Boolean minimization Next-state functions Logic decomposition Decomposed functions Technology mapping Gate netlist 4
x y z Specification x y z x+ z+ y+ y x z-
Signal Transition Graph (STG)
5
Token flow x y z x+ z+ y+ y x z 6
x+ z+ y+ y x State graph z y-
xyz
000 x+ z+ 100 y+ x 101 y+ 001 y+ 011 z x 111 110 z+ 010 7
z x y
Next-state functions (
x
y
)
xyz
000 x+ z+ 100 y+
x y z
y x 101 y+ 001 y+ 011 z x 111 110 z+ 010 8
Gate netlist
z x y
(
x
y
)
x y z
y x z 9
Design flow Specification (STG) Reachability analysis State Graph State encoding SG with CSC Boolean minimization Next-state functions Logic decomposition Decomposed functions Technology mapping Gate netlist 10
VME bus
Bus
Data Transceiver DSr DSw DTACK D LDS
VME Bus Controller
LDTACK Device DSr LDS LDTACK D DTACK
Read Cycle
11
LDS+ STG for the READ cycle DTACK DSr+ LDTACK+ D+ DTACK+ DSr D LDTACK LDS DSr DTACK D LDS
VME Bus Controller
LDTACK 12
Choice: Read and Write cycles DSr+ LDS+ DSw+ D+ LDTACK+ LDS+ DTACK D+ LDTACK LDTACK LDTACK+ DTACK DTACK+ DSr D LDS D LDS DTACK+ DSw 13
Choice: Read and Write cycles DTACK DSr+ LDS+ LDTACK+ D+ DTACK+ DSr D LDTACK LDS DSw+ D+ LDS+ LDTACK+ D DTACK+ DSw 14
Circuit synthesis Goal: Derive a hazard-free circuit under a given delay model and mode of operation 15
Speed independence Delay model Unbounded gate / environment delays Certain wire delays shorter than certain paths in the circuit Conditions for implementability: Consistency Complete State Coding Persistency 16
Design flow Specification (STG) Reachability analysis State Graph State encoding SG with CSC Boolean minimization Next-state functions Logic decomposition Decomposed functions Technology mapping Gate netlist 17
LDS+ STG for the READ cycle DTACK DSr+ LDTACK+ D+ DTACK+ DSr D LDTACK LDS DSr DTACK D LDS
VME Bus Controller
LDTACK 18
Binary encoding of signals LDTACK+ LDS+ DSr+ LDTACK DSr+ LDS DSr+ DTACK LDTACK DTACK LDTACK LDS DTACK LDS D+ D DTACK+ DSr 19
Binary encoding of signals 10 0 10 LDTACK+ 1011 0 D+ 100 0 0 LDS+ DSr+ LDTACK DSr+ DTACK LDTACK DTACK 101 1 LDS DSr+ 0 LDS DTACK 0 01 1 0 D LDTACK 0 11 00 LDS 0 1 1 1 0 DTACK+ DSr (DSr , DTACK , LDTACK , LDS , D) 20
Excitation / Quiescent Regions ER (LDS+) LDS+ QR (LDS-) QR (LDS+) LDS LDS LDS ER (LDS-) 21
1
1
10110 Next-state function
0
1
LDS+
0
0
LDS LDS LDS-
1
0
10110 22
Karnaugh map for LDS D LDTACK DTACK DSr 00 00
0
01 11 10
0 -
01
0 0
LDS = 0 11
-
10
1 0 -
D LDTACK DTACK DSr 00 00
-
01
-
11 10
0 -
01
1 0
LDS = 1 11
1
10
1 1 0/1?
23
Design flow Specification (STG) Reachability analysis State Graph State encoding SG with CSC Boolean minimization Next-state functions Logic decomposition Decomposed functions Technology mapping Gate netlist 24
Concurrency reduction 10110 DSr+ LDS+ DSr+ LDS DSr+ 10110 LDS LDS 25
Concurrency reduction LDS+ LDTACK+ DSr+ D+ LDTACK DTACK DTACK+ DSr LDS D 26
State encoding conflicts LDTACK+ 10110 LDS+ LDTACK LDS 10110 27
LDS+ Signal Insertion CSC+ LDTACK LDTACK+ 1011 0 1 LDS 101 1 00 DSr CSC D 28
Design flow Specification (STG) Reachability analysis State Graph State encoding SG with CSC Boolean minimization Next-state functions Logic decomposition Decomposed functions Technology mapping Gate netlist 29
Complex-gate implementation
LDS
D
csc
DTACK
D D
LDTACK
csc csc
DSr
(csc
LDTACK
) 30
Implementability conditions Consistency Rising and falling transitions of each signal alternate in any trace Complete state coding (CSC) Next-state functions correctly defined Persistency No event can be disabled by another event (unless they are both inputs) 31
Implementability conditions Consistency + CSC + persistency There exists a speed-independent circuit that implements the behavior of the STG (under the assumption that ay Boolean function can be implemented with one complex gate) 32
100
b
+
a-
000 Persistency
c+
001
b
+
a c a b c b
is this a pulse ?
Speed independence glitch-free output behavior under any delay 33
a a+ b+ a c+ d+ a+ b c d 0 000 a+ 1 0 00 b+ 1 100 a 01 0 0 c+ 011 0 d+ 0 111 a+ 1 1 11 b a 1 0 1 1 c 00 1 1 c a 000 1 1 001 d-
cd ab 00 00 0 01 0 11 1 10 01 0 11 0 1 1 1 10 0 1 1 0 000 a+ ER(d+) 1 0 00 b+ 1 100 a 01 0 0 c+ 011 0 d+ 0 111 a+ 1 1 11 b a 1 0 1 1 c 00 1 1 c ER(d-) a 000 1 1 001 d-
cd ab 00 00 0 01 0 11 1 10 01 0 11 0 1 1 1
d
c
ad
10 0 1 1 Complex gate 0 000 a+ 1 0 00 b+ 1 100 a 01 0 0 c+ 011 0 d+ 0 111 a+ 1 1 11 b a 1 0 1 1 c 00 1 1 c a 000 1 1 001 d-
Implementation with C elements
S R
C z • • • S+ z+ S R+ z R • • • •
S
(set) and
R
(reset) must be mutually exclusive •
S
must cover
ER(z+)
and must not intersect
ER(z-)
QR(z-)
•
R
must cover
ER(z-)
and must not intersect
ER(z+)
QR(z+)
37
cd ab 00 00 0 01 0 11 1 10 01 0 11 0 1 1 1 10 0 1 1
c a c S R
C d 0 000 a+ 1 0 00 b+ 1 100 a 01 0 0 c+ 011 0 d+ 0 111 a+ 1 1 11 b a 1 0 1 1 c 00 1 1 c a 000 1 1 001 d-
cd ab 00 00 0 01 0 11 1 10 01 0 11 0 1 1 1 10 0 1 1
c a b c S R
Monotonic covers C d 0 000 a+ 1 0 00 b+ 1 100 a 01 0 0 c+ 011 0 d+ 0 111 a+ 1 1 11 b a 1 0 1 1 c 00 1 1 c a 000 1 1 001 d-
C-based implementations
c S R
C d c C
a b c
b a d c a b weak d c a generalized C elements (gC) weak d 40
Speed-independent implementations Implementability conditions Consistency Complete state coding Persistency Circuit architectures Complex (hazard-free) gates C elements with monotonic covers ...
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z y w Synthesis exercise y z 1001 w y+ 1000 w z 0001 x+ w+ 1010 w y+ 0000 x+ 0101 z y+ x+ x 0010 x+ y+ 0100 0110 z+ z+ 1011 w+ 0011 x 0111 Derive circuits for signals
x
and
z
(complex gates and monotonic covers) 42
yz wx 00 00 1 01 1 11 10 0 1 01 1 1 0 1 Synthesis exercise 11 10 0 y z 1001 w y+ 1000 w z 0001 x+ 0 1010 w y+ 0000 x+ 0101 z 0 0 0010 x+ y+ 0100 0110 z+ Signal
x
1011 w+ 0011 x 0111 43
yz wx 00 00 0 01 0 11 1 10 0 01 0 0 1 1 Synthesis exercise 11 10 0 y z 1001 w y+ 1000 w z 0001 x+ 0 1010 w y+ 0000 x+ 0101 z 1 0 0010 x+ y+ 0100 0110 z+ Signal
z
1011 w+ 0011 x 0111 44
Logic decomposition: example y z 1001 w y+ 1000 w z 0001 x+ 1010 w y+ 0000 x+ 0101 z 0010 x+ y+ 0100 0110 z+ 1011 w+ 0011 x 0111 z y+ y z+ w x+ w+ x 45
Logic decomposition: example x y z y w z x w 0101 z w z C y z y yz=0 yz=1 x y C z 46
Logic decomposition: example
s=1
x y z 1001
s-
1011 y
s
z y+ 1000
s-
z 1001 w w+ w 1010
s-
y+ 1000 w z 0001 x+ 0011 x w 1010 w y+ 0000 x+ 0101 z 0111 z z C 0010 x+ y+ 0100
s+
x y C
s=0
z+ 0110 0111 y 47 w x y z
Logic decomposition: example
s=1
y y z 1001 1011
s s-
y+ 1000
s-
z 1001 w w+ 0011 z w 1010
s-
y+ 1000 w z 0001 x+ x 1010 w y+ 0000 x+ 0101 z y+ x+ 0111
s=0
0010 x+ y+ 0100
s+
z+
s+
w+ x z+ 0111 0110 48
Speed-independent Netlist LDS+ DTACK DTACK+ DSr LDS D DTACK LDTACK+ DSr+ D+ LDTACK D LDS map csc DSr LDTACK 49
Adding timing assumptions DTACK DSr+ LDS+ LDTACK+ D+ DTACK+ DSr D DTACK LDTACK LDS D LDTACK- before DSr+ SLOW DSr map csc LDS FAST LDTACK 50
Adding timing assumptions DTACK DSr+ LDS+ LDTACK+ D+ DTACK+ DSr D LDTACK LDS D LDTACK- before DSr+ DTACK LDS map csc DSr LDTACK 51
State space domain
DSr+
LDTACK- before DSr+
LDTACK-
52
State space domain
DSr+
LDTACK- before DSr+
LDTACK-
53
State space domain
DSr+
LDTACK- before DSr+
LDTACK Two more unreachable states
54
Boolean domain D LDTACK DTACK DSr 00 00
0
01 11 10
0 -
01
0 0
LDS = 0 11
-
10
1 0 -
D LDTACK DTACK DSr 00 00
-
01
-
11 10
0 -
01
1 0
LDS = 1 11
1
10
1 1 0/1?
55
Boolean domain LDS = 0 LDS = 1 D LDTACK DTACK DSr 00 00 01 11
0
10
0 -
01
0 0
11
1 -
10
One more DC vector for all signals
D LDTACK DTACK DSr 00 00 01
-
01
1
11
1
10
1 1
11 10
0 0 1 One state conflict is removed
56
Netlist with one constraint DTACK DSr+ LDS+ LDTACK+ D+ DTACK+ DSr D LDTACK LDS D DTACK LDS map csc DSr LDTACK 57
Netlist with one constraint DTACK DSr+ LDS+ LDTACK+ D+ DTACK+ DSr D DTACK LDTACK LDS D
TIMING CONSTRAINT LDTACK- before DSr+
DSr LDS LDTACK 58
Conclusions STGs have a high expressiveness power at a low level of granularity (similar to FSMs for synchronous systems) Synthesis from STGs can be fully automated Synthesis tools often suffer from the state explosion problem (symbolic techniques are used) The theory of logic synthesis from STGs can be found in: J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno and A. Yakovlev,
Logic Synthesis of Asynchronous Controllers and Interfaces
, Springer Verlag, 2002.
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