Transcript Asynchronous Interface Specification, Analysis and Synthesis

Asynchronous Circuit Verification
and Synthesis with Petri Nets
J. Cortadella
Universitat Politècnica
de Catalunya, Barcelona
Thanks to: Michael Kishinevsky (Intel Corporation)
Alex Kondratyev (The University of Aizu)
Luciano Lavagno (Politecnico di Torino)
Enric Pastor (Universitat Politècnica de Catalunya)
Alex Taubin (The University of Aizu)
Alex Yakovlev (University of Newcastle upon Tyne)
Motivation
 Interfaces
are often asynchronous
 Subsystems with different clocks often
want to talk to each other
 Self timing provides functional and
temporal modularity
 … and no clock skew, low power,
low EMI, average performance, ...
Why Petri nets ?
 Formal
model to specify causality,
concurrency and choice between events
 Simple
enough to easily derive state-level
information (logic synthesis)

Powerful enough to implicitly represent a
large state space
Outline
 Design
flow
 Synthesis
– Specification
– State encoding
– Logic decomposition
 Synthesis
of Petri nets
 Formal verification
Specification
(STG)
Reachability analysis
State Graph
State encoding
SG with
CSC
Design
flow
Boolean minimization
Next-state
functions
Logic decomposition
Decomposed
functions
Technology mapping
Gate netlist
x
y
x
z
y
z
z+
x+
x-
y+
z-
y-
Signal Transition Graph (STG)
x
y
z
z+
x+
x-
y+
y-
z-
xyz
000
x+
z+
x+
z+
xy+
y-
z-
y-
x-
100
y+
101
110
y+
z+
001
111
y+
x-
011
z-
010
Synchronous
xyz
000
x+
z+
Current
state
Next
state
y-
Asynchronous
x-
110
y+
z+
001
111
x-
011
zNext
state
y+
101
y+
Current
state
100
010
xyz
000
Next-state functions
x+
x  z  (x  y)
y  zx
z  x  y z
z+
y-
x-
100
y+
101
110
y+
z+
001
111
y+
x-
011
z-
010
Next-state functions
x  z  (x  y)
y  zx
z  x  y z
x
y
z
Specification
(STG)
Reachability analysis
State Graph
State encoding
SG with
CSC
Design
flow
Boolean minimization
Next-state
functions
Logic decomposition
Decomposed
functions
Technology mapping
Gate netlist
VME bus
Bus
DSr
Data
Transceiver
LDS
LDTACK
Device
D
DSr
DSw
LDS
VME Bus
Controller LDTACK
D
DTACK
DTACK
Read Cycle
STG for the READ cycle
DSr+
LDS+
LDTACK+
DTACK-
D+
DTACK+
LDTACK-
LDS-
D
DSr
DTACK
VME Bus
Controller
LDS
LDTACK
DSr-
D-
Choice: Read and Write cycles
LDTACK-
LDS-
DSr+
DSw+
LDS+
D+
LDTACK+
LDS+
D+
DTACK-
DTACK-
LDTACK+
DTACK+
D-
DSr-
DTACK+
D-
DSw-
LDTACK-
LDS-
Choice: Read and Write cycles
LDTACK-
LDS-
DSr+
DSw+
LDS+
D+
LDTACK+
LDS+
D+
DTACK-
DTACK-
LDTACK+
DTACK+
D-
DSr-
DTACK+
D-
DSw-
LDTACK-
LDS-
Circuit synthesis
 Goal:
– Derive a hazard-free circuit
under a given delay model and
mode of operation
Modes of operation

Fundamental mode
– Single-input changes
– Multiple-input changes

Current
state
Next
state
Input / Output mode
– Concurrency
circuit / environment
STG for the READ cycle
DSr+
LDS+
LDTACK+
DTACK-
D+
DTACK+
LDTACK-
LDS-
D
DSr
DTACK
VME Bus
Controller
LDS
LDTACK
DSr-
D-
Speed independence
 Delay
model
– Unbounded gate / environment delays
– Certain wire delays shorter than certain
paths in the circuit
 Conditions
for implementability:
– Consistency
– Complete State Coding
– Output persistency
Other synthesis approaches
 Burst-mode
machines
– Mealy-like FSMs
– Fundamental mode (slow environment)
 VLSI
programming
– Syntax-directed translation from CSP
(“Communicating Sequential Processes”)
– No logic synthesis
– Circuit size ~ Size of the specification
Specification
(STG)
Reachability analysis
State Graph
State encoding
SG with
CSC
Design
flow
Boolean minimization
Next-state
functions
Logic decomposition
Decomposed
functions
Technology mapping
Gate netlist
State Graph (Read cycle)
DSr+
LDS+
LDTACKDSr+
LDS-
LDTACK+
DSr+
D+
DTACK-
LDTACKDTACK-
LDS-
LDS-
DTACK-
DDTACK+
DSr-
LDTACK-
Binary encoding of signals
DSr+
LDS+
LDTACKDSr+
LDS-
LDTACK+
DSr+
D+
DTACK-
LDTACKDTACK-
LDS-
LDS-
DTACK-
DDTACK+
DSr-
LDTACK-
Binary encoding of signals
DSr+
10000
LDS+
LDTACK-
LDTACK-
DSr+
10010
LDS-
LDTACK+
DTACK-
LDS-
DSr+
10110
D+
DTACK-
10110
LDTACK-
01100
LDS-
DTACK-
01110
00110
D-
DTACK+
DSr-
(DSr , DTACK , LDTACK , LDS , D)
Excitation / Quiescent Regions
ER (LDS+)
LDS+
QR (LDS-)
LDS-
QR (LDS+)
LDS-
LDS-
ER (LDS-)
Next-state function
01
LDS+
11
00
LDS-
LDS-
LDS-
10
10110
10110
Karnaugh map for LDS
LDS = 1
LDS = 0
D
LDTACK
DTACK
DSr
00
01
11
10
D
LDTACK
DTACK
DSr
00
01
11
10
00
0
0
-
1
00
-
-
-
1
01
-
-
-
-
01
-
-
-
-
11
-
-
-
-
11
-
1
1
1
10
0
0
-
0
10
0
0
- 0/1?
Specification
(STG)
Reachability analysis
State Graph
State encoding
SG with
CSC
Design
flow
Boolean minimization
Next-state
functions
Logic decomposition
Decomposed
functions
Technology mapping
Gate netlist
Concurrency reduction
DSr+
LDS+
DSr+
LDSDSr+
10110
10110
LDS-
LDS-
Concurrency reduction
DSr+
LDS+
LDTACK+
D+
LDTACK-
DTACK-
DTACK+
DSr-
D-
LDS-
(See today’s presentation in this workshop for more details)
State encoding conflicts
LDS+
LDTACK+
LDTACK-
LDS-
10110
10110
Signal Insertion
CSC+
LDS+
LDTACK+
LDTACK-
LDS-
101101
101100
D-
DSr-
CSC-
Specification
(STG)
Reachability analysis
State Graph
State encoding
SG with
CSC
Design
flow
Boolean minimization
Next-state
functions
Logic decomposition
Decomposed
functions
Technology mapping
Gate netlist
Complex-gate implementation
LDS  D  csc
DTACK  D
D  LDTACK csc
csc  DSr  (csc LDTACK )
Specification
(STG)
Reachability analysis
State Graph
State encoding
SG with
CSC
Design
flow
Boolean minimization
Next-state
functions
Logic decomposition
Decomposed
functions
Technology mapping
Gate netlist
Hazards
abcx
1000
b+
1100
a0100
c+
0110
0
1
1
0
0
1
a
b
c
x
0
Hazards
abcx
1000
1000
b+
1100
a0100
0100
c+
0110
1
0
a
z
0
1
1
0
b
0
1
c
x
0
1
Decomposition
 Global


acknowledgement
Generating candidates
Hazard-free signal insertion
– Event insertion
– Signal insertion
Global acknowledgement
d-
b+
d+
y+
a-
y-
c+
d-
c-
d+
z-
b-
z+
c+
a+
c-
c
b
a
z
a
b
d
y
How about 2-input gates ?
d-
b+
d+
y+
a-
y-
c+
d-
c-
d+
z-
b-
z+
c+
a+
c-
c
b
a
z
a
b
d
y
How about 2-input gates ?
d-
b+
d+
y+
a-
y-
c+
d-
c-
d+
z-
b-
z+
c+
a+
c-
c
z
b
a
a
b
d
y
How about 2-input gates ?
d-
b+
d+
y+
a-
y-
c+
d-
c-
d+
z-
b-
z+
c+
a+
c-
c 0
b
0 z
a
a
b
d
y
How about 2-input gates ?
d-
b+
d+
y+
a-
y-
c+
d-
c-
d+
z-
b-
z+
c+
a+
c-
c
b
a
z
a
y
b
d
How about 2-input gates ?
d-
b+
d+
y+
a-
y-
c+
d-
c-
d+
z-
b-
z+
c+
a+
c-
c
z
a
b
y
d
Strategy for correct logic
decomposition
 Each
decomposition defines a new
internal signal of the circuit
 Method: Insert new internal signals such
that
– After resynthesis,
some large gates are decomposed
– The new specification is hazard-free under
unbounded gate delays
Decomposition example
1001
zy+
1010
yw-
1000
0001
w- z-
w- y+
0010
0000
0110
1011
w+
x+
0101
x+ z-
0011
0100
x-
x+ y+
y-
z+
0111
z-
w-
w+
y+
x+
x-
z+
1001
z-
y+
1010
yw-
1000
0001
w- z-
w- y+
0010
0000
0110
yz=0
1011
x+
0100
z+
w
y
z
w+
0101
x+ z-
x+ y+
x
y
z
x
w
0011
w
x0111
yz=1
z
x
y
z
y
C
y
C
z
x
s=1
zy+
1010
1000
s- y+
1001
s- z1000
y1011
s1001
w-
0001
w- zx+
x+ y+
s=0
0110
s
y
z
w+
1010
0000
0101
w- y+
x+ z0010
w
0100
z+
w
0011
x-
x
w
z
z
C
y
C
z
0111
s+
0111
x
y
y
s=1
zy+
1010
1000
s- y+
1001
s- z1000
y-
s1001
w+
0001
w- zx+
x+ y+
s=0
0110
s-
w-
1010
0000
0101
w- y+
x+ z0010
y-
1011
0100
z+
0011
z-
w-
w+
y+
x+
x-
x0111
s+
0111
z+
s+
1001
z-
y+
1010
yw-
1000
0001
w- z-
w- y+
0010
0000
0110
yz=0
1011
x+
0100
z+
w
y
z
w+
0101
x+ z-
x+ y+
x
y
z
x
w
0011
w
z
x0111
yz=1
x
y
z
y
C
y
C
z
s=1
1001
s-
zy+
1000
1001
yw+
0001
w- zx+
x+ y+
s=0
0110
s-
w-
1010
0000
0101
w- y+
x+ z0010
y-
1011
0100
z+
0011
z-
w-
w+
y+
x+
x-
x0111
s+
0111
z+
z- is delayed by the new transition s- !
s+
x
1001
z-
y+
1010
yw-
1000
0001
w- z-
w- y+
0010
0000
0110
yz=0
y
z
w+
x+
0101
x+ z-
x+ y+
1011
w
0100
z+
x
w
0011
w
z
x0111
yz=1
y
x
y
z
C
y
C
z
Signal insertion for function F
Insertion by input borders
F+
F=0
F=1
FState Graph
Event insertion
SR(x)
b
a
x x
a
x
b
ER(x)
x
c
Properties to preserve
a
b
a
b
a
b
a
a is
disabled by b
= hazards
b
x
x a b
a is
persistent
a
b
b
a
b
b
x
a
Interactive design flow
Reachability
analysis
Transition
System
Petri Net
(STG)
Transformations
+ Synthesis
Transition
System
Theory of regions
(Ehrenfeucht 90, Nielsen 92)
a
a
c
a
a
c
b
b
b
c
b
Synthesis of Petri Nets
a
c
a
c
b
b
b
a
c
b
c
Excitation closure
a
c
a
c
b
b
b
a
c
b
c
Label splitting
d
a
b
c
b
d
d
a
d
b
c
c
d
b
b
b
Formal verification
 Implementability
properties
– Consistency, persistency, state coding …
 Behavioral
properties (safeness, liveness)
– Mutual exclusion, “ack” after “req”, …
 Equivalence
checking
– Circuit  Specification
– Circuit < Specification
Property verification: consistency
d+
c+
a+
b-
d-
a+
a-
b+
c-
a-
Specification
Property
Failure if a+ enabled in specification and
a- enabled in property (or viceversa)
Correctness: environment  circuit
d+
Circuit
c+
a
b
a+
b-
d-
c
b+
d
c-
a-
Environment
Failure: circuit produces an
event unexpected (not enabled)
by the environment
Fighting the state explosion
 Symbolic
methods (BDDs)
 Partial order reductions
 Petri net unfoldings
 Structural theory (invariants)
Fighting with state explosion
p1
p1
0
1
p1 p2 p3
p2
p3
p1 p2 p3
p2
p2
0
p1 p2 p3
1
p3
1
0
1
00
0
p3
1
1
Representing Markings
p2 + p3 + p5 = 1
p0 + p1 + p4 + p5 = 1
p2
p3
p4
p1
p5
p0
Place encoding
p2  v0 v1
p3  v0 v1
p5  v0
p0  v2 v3
p1  v2 v3
p4  v2
{ p0, p3 }  v0 v1 v2 v3
Summary
 Asynchronous
–
–
–
–

design is applicable to
asynchronous interfaces
high-performance computing
low-power design
low-emission design
There is an increased interest of few, but
large scale companies: Intel, Philips, Sun,
Sharp, ARM, HP, Cogency
Summary (continued)
 Asynchronous
circuits are more difficult to
design than synchronous
 Formal models and CAD support are
essential
 Petri nets have been one of the most
successful formalisms for modeling
asynchronous circuits
 Most steps of the design process covered by
this tutorial are supported by the tool Petrify