Transcript Introduction to basic concepts on asynchronous circuit design

Introduction to
asynchronous circuit design:
specification and synthesis
Part II:
Synthesis of control circuits
from STGs
Outline
•
•
•
•
•
•
Overview of the synthesis flow
Specification
State graph and next-state functions
State encoding
Implementability conditions
Speed-independent circuit
– Complex gates
– C-element architecture
Specification
(STG)
Reachability analysis
State Graph
State encoding
Design
flow
SG with
CSC
Boolean minimization
Next-state
functions
Logic decomposition
Decomposed
functions
Technology mapping
Gate netlist
x
y
x
z
y
z
z+
x+
x-
y+
z-
y-
Signal Transition Graph (STG)
x
y
z
z+
x+
x-
y+
y-
z-
xyz
000
x+
z+
x+
z+
xy+
y-
z-
y-
x-
100
y+
101
110
y+
z+
001
111
y+
x-
011
z-
010
xyz
000
Next-state functions
x+
x  z  (x  y)
y  zx
z  x  y z
z+
y-
x-
100
y+
101
110
y+
z+
001
111
y+
x-
011
z-
010
Next-state functions
x  z  (x  y)
y  zx
z  x  y z
x
y
z
Specification
(STG)
Reachability analysis
State Graph
State encoding
Design
flow
SG with
CSC
Boolean minimization
Next-state
functions
Logic decomposition
Decomposed
functions
Technology mapping
Gate netlist
VME bus
Bus
DSr
Data
Transceiver
LDS
LDTACK
Device
D
DSr
DSw
LDS
VME Bus
Controller LDTACK
D
DTACK
DTACK
Read Cycle
STG for the READ cycle
DSr+
LDS+
LDTACK+
DTACK-
D+
DTACK+
LDTACK-
LDS-
D
DSr
DTACK
VME Bus
Controller
LDS
LDTACK
DSr-
D-
Choice: Read and Write cycles
LDTACK-
LDS-
DSr+
DSw+
LDS+
D+
LDTACK+
LDS+
D+
DTACK-
DTACK-
LDTACK+
DTACK+
D-
DSr-
DTACK+
D-
DSw-
LDTACK-
LDS-
Choice: Read and Write cycles
LDTACK-
LDS-
DSr+
DSw+
LDS+
D+
LDTACK+
LDS+
D+
DTACK-
DTACK-
LDTACK+
DTACK+
D-
DSr-
DTACK+
D-
DSw-
LDTACK-
LDS-
Choice: Read and Write cycles
LDTACK-
LDS-
DSr+
DSw+
LDS+
D+
LDTACK+
LDS+
D+
DTACK-
DTACK-
LDTACK+
DTACK+
D-
DSr-
DTACK+
D-
DSw-
LDTACK-
LDS-
Choice: Read and Write cycles
LDTACK-
LDS-
DSr+
DSw+
LDS+
D+
LDTACK+
LDS+
D+
DTACK-
DTACK-
LDTACK+
DTACK+
D-
DSr-
DTACK+
D-
DSw-
LDTACK-
LDS-
Circuit synthesis
• Goal:
– Derive a hazard-free circuit
under a given delay model and
mode of operation
Speed independence
• Delay model
– Unbounded gate / environment delays
– Certain wire delays shorter than certain paths in the
circuit
• Conditions for implementability:
– Consistency
– Complete State Coding
– Persistency
Specification
(STG)
Reachability analysis
State Graph
State encoding
Design
flow
SG with
CSC
Boolean minimization
Next-state
functions
Logic decomposition
Decomposed
functions
Technology mapping
Gate netlist
STG for the READ cycle
DSr+
LDS+
LDTACK+
DTACK-
D+
DTACK+
LDTACK-
LDS-
D
DSr
DTACK
VME Bus
Controller
LDS
LDTACK
DSr-
D-
Binary encoding of signals
DSr+
LDS+
LDTACKDSr+
LDS-
LDTACK+
DSr+
D+
DTACK-
LDTACKDTACK-
LDS-
LDS-
DTACK-
DDTACK+
DSr-
LDTACK-
Binary encoding of signals
DSr+
10000
LDS+
LDTACK-
LDTACK-
DSr+
10010
LDS-
LDTACK+
DTACK-
LDS-
DSr+
10110
D+
DTACK-
10110
LDTACK-
01100
LDS-
DTACK-
01110
00110
D-
DTACK+
DSr-
(DSr , DTACK , LDTACK , LDS , D)
Excitation / Quiescent Regions
ER (LDS+)
LDS+
QR (LDS-)
LDS-
QR (LDS+)
LDS-
LDS-
ER (LDS-)
Next-state function
01
LDS+
11
00
LDS-
LDS-
LDS-
10
10110
10110
Karnaugh map for LDS
LDS = 1
LDS = 0
D
LDTACK
DTACK
DSr
00
01
11
10
D
LDTACK
DTACK
DSr
00
01
11
10
00
0
0
-
1
00
-
-
-
1
01
-
-
-
-
01
-
-
-
-
11
-
-
-
-
11
-
1
1
1
10
0
0
-
0
10
0
0
- 0/1?
Specification
(STG)
Reachability analysis
State Graph
State encoding
Design
flow
SG with
CSC
Boolean minimization
Next-state
functions
Logic decomposition
Decomposed
functions
Technology mapping
Gate netlist
Concurrency reduction
DSr+
LDS+
DSr+
LDSDSr+
10110
10110
LDS-
LDS-
Concurrency reduction
DSr+
LDS+
LDTACK+
D+
LDTACK-
DTACK-
DTACK+
LDS-
DSr-
D-
State encoding conflicts
LDS+
LDTACK+
LDTACK-
LDS-
10110
10110
Signal Insertion
CSC+
LDS+
LDTACK+
LDTACK-
LDS-
101101
101100
D-
DSr-
CSC-
Specification
(STG)
Reachability analysis
State Graph
State encoding
Design
flow
SG with
CSC
Boolean minimization
Next-state
functions
Logic decomposition
Decomposed
functions
Technology mapping
Gate netlist
Complex-gate implementation
LDS  D  csc
DTACK  D
D  LDTACK csc
csc  DSr  (csc LDTACK )
Implementability conditions
• Consistency
– Rising and falling transitions of each signal
alternate in any trace
• Complete state coding (CSC)
– Next-state functions correctly defined
• Persistency
– No event can be disabled by another event
(unless they are both inputs)
Implementability conditions
• Consistency + CSC + persistency
• There exists a speed-independent circuit
that implements the behavior of the STG
(under the assumption that ay Boolean function
can be implemented with one complex gate)
Persistency
100
a-
000
c+
001
b+
b+
a
c
b
a
c
b
is this a pulse ?
Speed independence  glitch-free output behavior under any delay
a+
0000
a+
b+
1000
b+
1100
a-
a-
0100
c+
c+
0110
d+
d+
0111
a+
a+
1111
b-
b-
1011
a-
a-
cd-
0011
c-
1001
c- a-
0001
d-
ab
cd
00
00
0
01
0
11
0
0000
10
a+
1000
0
b+
1100
01
11
1
0
1
1
1
1
a-
0100
c+
ER(d+)
0110
d+
10
0111
1
a+
1111
b-
1011
a-
0011
ER(d-)
c-
1001
c- a-
0001
d-
ab
cd
00
00
01
0
0
11
0
10
0
0000
a+
1000
b+
1100
01
11
1
0
1
1
1
1
a-
0100
c+
0110
d+
10
1
0111
a+
1111
d  ad  ac
b-
1011
a-
0011
Complex gate
c-
1001
c- a-
0001
d-
Implementation with C elements
S
R
C
z
• • •  S+  z+  S-  R+  z-  R-  • • •
• S (set) and R (reset) must be mutually exclusive
• S must cover ER(z+) and must not intersect ER(z-)  QR(z-)
• R must cover ER(z-) and must not intersect ER(z+)  QR(z+)
ab
cd
00
00
0
01
0
11
0000
10
0
a+
1000
0
b+
1100
01
11
1
0
1
1
a-
0100
c+
1
1
0110
d+
10
0111
1
a+
1111
b-
c
ac
1011
S
R
C
d
a-
0011
c-
1001
c- a-
0001
d-
0000
a+
1000
b+
1100
a-
but ...
0100
c+
0110
d+
0111
a+
1111
b-
c
ac
1011
S
R
C
d
a-
0011
c-
1001
c- a-
0001
d-
Assume that R=ac has an unbounded delay
Starting from state 0000 (R=1 and S=0):
0000
a+
1000
b+
1100
a+ ; R- ; b+ ; a- ; c+ ; S+ ; d+ ;
a-
0100
c+
R+ disabled (potential glitch)
0110
d+
0111
a+
1111
b-
c
ac
1011
S
R
C
d
a-
0011
c-
1001
c- a-
0001
d-
ab
cd
00
00
0
01
0
11
0000
10
0
a+
1000
0
b+
1100
01
11
1
0
1
1
a-
0100
c+
1
1
0110
d+
10
0111
1
a+
1111
b-
c
ab c
1011
S
R
C
d
a-
0011
1001
c- a-
0001
Monotonic covers
c-
d-
C-based implementations
c
ab c
c
S
R
c
d
C
C
b
a
d
weak
d
c
weak
d
a
b
a
generalized C elements (gC)
Speed-independent implementations
• Implementability conditions
– Consistency
– Complete state coding
– Persistency
• Circuit architectures
– Complex (hazard-free) gates
– C elements with monotonic covers
– ...
Synthesis exercise
y-
1001
z-
y+
zy+
wx+
z+
w+
x-
1010
yw-
1000
0001
w- z-
w- y+
0010
0000
w+
x+
0101
x+ z-
0011
0100
x-
x+ y+
0110
1011
z+
0111
Derive circuits for signals x and z (complex gates and monotonic covers)
Synthesis exercise
yz
z-
wx
00
1001
00
1
01
1
11
-
w-
1011
10
0
y+
1010
01
1
1
-
0
11
0
0
-
0
10
1
1
-
0
Signal x
y-
1000
0001
w- z-
w- y+
0010
0000
x+
0101
x+ z-
0011
0100
x-
x+ y+
0110
w+
z+
0111
Synthesis exercise
yz
z-
wx
00
1001
00
0
01
0
11
-
w-
1011
10
0
y+
1010
01
0
0
-
0
11
1
1
-
1
10
0
1
-
0
Signal z
y-
1000
0001
w- z-
w- y+
0010
0000
x+
0101
x+ z-
0011
0100
x-
x+ y+
0110
w+
z+
0111