Transcript Diskreetne Matemaatika. S.

IAY 0600
Digitaalsüsteemide disain
Course Overview
Alexander Sudnitson
Tallinn University of Technology
Administrative
Aleksander Sudnitsõn
Arvutitehnika instituut, dotsent
IT-309
[email protected]
www.pld.ttu.ee/~alsu
IAY0600 Digitaalsüsteemide disain (erikursus)
IAY0600 Digitaalsüsteemide disain (PRAKTIKUM)
IAY0120 ARVUTITEHNIKA PROJEKT
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Administrative
Loengute õppetöö keel: inglise
Loengud:
neljapäeviti
14.00 - 15.30
Praktikum: IT-307 Dimitri Mihhajlov
16.00 - 17.30
esemine regulaarne praktikum toimub
18.02.2010 (pärast registreerimist)
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Hindamine
Teoreetiliste teadmiste osakaal eksamil on
40% hindest ja projekteerimisülesannete
tulemuste demonstratsioon koos lahenduste
seletuskirjaga annab 60% eksamihindest.
“LEARNING BY DOING”
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Õppeaine sisu lühikirjeldus
Digitaalsüsteemide projekteermis-metoodika
VHDL ja prgrammeeritava loogika (FPGA) abil.
Realiseerimine väliprogrammeeritaval loogikal
(FPGA).
Digitaalseadmete kiire prototüüpimine.
Asünkroonsete süsteemide põhialused
(süsteemne vaade).
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Õppekirjandus
Iga tudeng saab komplekti slaide enne
loengut.
K. L. Short, VHDL for Engineers, Pearson Education,
Inc., 2009.
Sparso J. and Furber S. Principles of Asynchronous
Circuit Design: a Systems Perspective. Boston:
Kluwer, 2001.
P.P. Chu, FPGA Prototyping Using VHDL Examples:
Xilinx Spartan-3 Version, Jonh, Willey & Sons, 2008.
J. O. Hamblen, T.S. Hall, and M. D. Furman, Rapid
Prototyping of Digital Systems, Springer, 2007.
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IAY 0600
Digitaaltehnika erikursus
VHDL/PLD Design Methodology
Alexander Sudnitson
Tallinn University of Technology
Digital System
A discrete system is a system in which signals have a finite number
of discrete values.
(This contrasts with analog systems, in which signals have values
from an infinite set).
Inputs
Discrete
System
Outputs
Any finite number of discrete values can be represented by a vector
of signals with just two values. Such a signal, which takes only two
values, is called a digital signal (or binary, or logic), and any device
that processes digital signals is called a digital device.
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Design process
The design process consists of obtaining an implementation that
satisfies the specification of a system.
Specification
(behaviour)
Analysis (verification)
Synthesis
Implementation
(structure)
The analysis of a system has an objective the determination of its
specification from an implementation.
The synthesis consists of obtaining an implementation that satisfies
the specification of a system
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Different design views
Systems can be described from different points of view:
Behavior: what does it do?
Structure: what is it composed of?
Functional properties: how do I interface to it?
Physical properties: how fast is it?
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Design Representation
Three different domains of description:
A behavioral or functional representation is one that looks at the design
as a black box. A behavioral representation describes the functionality but
not the implementation of a given design, defining the black box’s
response to any combination of input values but without describing a way
to design or build the black box using the given components.
A structural representation is one that the black box as a set of
components and their connections. It specifies the product’s implementation
without explicit reference to its functionality.
In some cases, the functionality could be derived from that of its
interconnected components.
A physical representation is one that specifies the physical
characteristics of the black box, providing the dimensions and locations
of each component and connection contained in the structural description.
The physical representation is used to describe the design after it has been
manufactured, specifying its weight, size, heat dissipation, power
consumption and the position of each input or output pin.
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Modified Y Chart: levels of abstruction
Behavior
Description
Structural
Description
System
Processes
Programmable
cores, IPs, ASICs
Architectural
Algorithm
Dataflow
Processor, Memory,
Peripheral interface
Register Transfer
(RTL)
Registers, Adders,
Multipliers, etc.
Logic
Boolean equations
Logic netlist,
Schematic
View
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Timing units at different levels
Behavior
Description
Structural
Description
Time Units
Comuncation Transaction
Processes
Algorithm
Computation Step
Dataflow
Boolean equations
Clock Cycle
Delay
Programmable
cores, IPs, ASICs
Processor, Memory,
Peripheral interface
Registers, Adders,
Multipliers, etc.
Logic netlist,
Schematic
View
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Modified Y Chart : this course area
Synthesis
Behavior
Description
Analysis
Structural
Description
Algorithm
Processor, Memory,
Peripheral interface
Dataflow / RTL
Registers, Adders,
Multipliers, etc.
Boolean equations
Logic netlist,
Schematic
View
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Modified Y Chart: transformations
Behavior
Description
Algorithm
Structural
Description
Algorithmic
Register-Transfer
Dataflow
Boolean equotions
Transformations
Processor, Memory,
Peripheral interface
Registers, Adders,
Multipliers, etc.
Logic
Logic netlist,
Schematic
View
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Chart supporting synthesis activity
Behavior
Description
Structural
Description
Algorithmic level
of abstraction
Behavioral
synthesis
Register-transfer
level of abstraction
RTL
synthesis
Logic level of
abstraction
Logic
synthesis
View
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Example: HalfAdder
Behavior
A B
Structure
Sum Carry
0 0
0
0
0 1
1
0
1 0
1
0
1 1
0
1
A
B
A
Sum = ¬A&B  A&¬B
=AB
B
Sum
HalfAdder
Carry

Sum
&
Carry
Carry = A & B
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Example: HalfAdder Behavioral Description
A
B
Sum
Sum = ¬A&B  A&¬B
=AB
Carry
Carry = A & B
HalfAdder
entity HALFADDER is
port(A, B: in bit; SUM, CARRY: out BIT);
end HALFADDER;
architecture RTL of HALFADDER is
begin
SUM <= A xor B;
CARRY <= A and B;
end RTL;
This is data flow behavioral description
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Design flow for VHDL/PLD design methodology
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The half-adder UUT and its testbench
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