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ESL and High-level Design: Who Cares? Anmol Mathur CTO and co-founder, Calypto Design Systems 2 3 Trends in Applications and Processor Design 4 Trends Driven by Consumer Electronics • Time-to-market is king! – Ability to re-target designs to new technology nodes – Ability to turn around ASICs in 3 month cycles • Flexible architectures – Allow same semiconductor part to live in multiple design generations • Low power designs – System-level and micro-architectural decisions impact power very significantly • Software is the queen! – Key differentiation in consumer products is via applications – Early software development is key 5 Move to System-level Design Optimization • Performance • Power / battery life • Design updates Economics • Development Cost • Time to Revenue • Re-spin reduction Complexity System Level Design • Increasing design size • HW / SW co-design • Verification testbench Productivity • Design reuse • Platform design • Optimization Design tools to leverage system-level models for RTL design and verification are needed 6 Usage of System Level Model Functional reference model Faster Simulation Platform for software development SLM to RTL Flows System Level Model Architectural and Performance Analysis 7 (High Level Synthesis) Algorithmic SLM to RTL Gap Process Flow SLM Manual Process Micro-architecture RTL Imp. User Control Broad Control 8 Limited Control Broad Control • Greater accuracy of power analysis requires detailed layout information 9 Accurate Switching Activity • Greater power savings opportunities at higher levels of abstraction Accurate Capacitance Power Dilemma Status of High-level Modeling Today • Majority of design teams still using raw C/C++ – Proprietary modeling of simulation time – Simulation speed and ease of coding are key criteria • System-model and RTL partitioning is not consistent – Hard to use system-models for RTL verification • System-level modeling and RTL teams do not talk! • Several different system models at differing levels of abstraction often exist – Different level of interface/timing accuracy – Different levels of computational accuracy • Diverse/non-standard modeling makes the space very fragmented – Very hard to build tools for verification/synthesis 10 SLM to RTL Flows System Designer Manual SLM to RTL DESIGN FLOW Algorithm Functional Description System Level Model Floating Point Model SLM TO RTL HLS DESIGN FLOW Algorithm Functional Description Floating Point Model Hardware Designer Fixed Point Model Fixed Point C++ Model Micro-architecture Definition Constraints High Level Synthesis RTL Synthesis Manual Methods RTL Design + RTL Area/Timing Optimization Vendor Precision RTL or DC ASIC or FPGA Vendor Hardware ASIC/FPGA 11 Logic Analyzer Logic Analyzer Hardware ASIC/FPGA RTL Synthesis Place & Route Place & Route + Replaces manual RTL creation with automation Connects system domain to hardware design Technology based design space exploration. Up to 20x reduction in RTL creation SLM to RTL Flow Target System Analysis Algorithm Technology files (Standard Cells + RAM cuts) FPGA Netlist Design model C/C++ SystemC FPGA High Level Synthesis Formal Proof (SEC) 12 FPGA synthesis RTL RTL to layout GDS2 ASIC Making ESL/HLM a Reality • Standardized levels of abstraction in system-level models – SystemC 2.0 starting to do that • Consistency between system-level models and RTL – Coherent system-level and RTL design teams • Tool eco-system to link system-level and RTL – System-level model validation – Hardware-software co-simulation – High-level synthesis – Sequential equivalence checking – Sequential/micro-architectural power optimizations at RTL and micro-architectural levels 13 www.calypto.com