Transcript DESIGN VERIFICATION

Finite State Machines
VHDL ET062G & ET063G Lecture 6
Najeem Lawal 2012
FINITE STATE MACHINES
OUTLINE
– Range Sensor display
– FSM in VHDL
• Medvedev FSM
• Moore FSM
• Mealy FSM
– FSMD – FSM and Data path
RANGE SENSOR DISPLAY
639
0
0
1. Specify the number of rows
2. Specify the location of the display
3. Determine the effective number of
bits for range sensor data
300
50
400
301
64
40
20
364
479
Najeem Lawal, 2012
VHDL ET062G & ET063G
Lecture 6
3
RANGE SENSOR DISPLAY
639
0
0
1. Specify the number of rows
2. Specify the location of the display
3. Determine the effective number of
bits for range sensor data
1.
400
301
2 counters
1. Column counter
to assess the content of the memory
2. Row counter
to know what to display
2.
300
50
What do you need
64
40
20
364
Comparator
479
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VHDL ET062G & ET063G
Lecture 6
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RANGE SENSOR DISPLAY
639
0
0
1. Specify the number of rows
2. Specify the location of the display
3. Determine the effective number of
bits for range sensor data
if (vcount > 300 and vcount < 365) then
if ((vcount - 300) >= (64 - pixel_data(7 downto 2))) then
red_out <= "111";
green_out<= "111";
blue_out <= "11";
400
301
64
else
red_out <= "000";
green_out<= "000";
blue_out <= "00";
300
50
40
20
364
end if;
else
red_out <= red_in;
green_out <= green_in;
blue_out <= blue_in;
479
end if;
Najeem Lawal, 2012
VHDL ET062G & ET063G
Lecture 6
5
RANGE SENSOR DISPLAY
639
0
0
1. Specify the number of rows
2. Specify the location of the display
3. Determine the effective number of
bits for range sensor data
To solve this problem
1. use if statements
2. use case statements
3. or combine into FSM
300
50
400
301
64
40
20
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Najeem Lawal, 2012
VHDL ET062G & ET063G
Lecture 6
6
USE CASES
STUDENT PROJECT PRESENTATIONS
– Farid
– Ashkan
– Patrick
HOW THE SOLVED
– Range sensor
– Edge detection
– Sliding window
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VHDL ET062G & ET063G
Lecture 5
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DESIGN OF STATE MACHINES
Develop a state graph that captures the problem
MANUAL DESIGN WORK FLOW:
Develop a solution state graph
Coding of states
Select register elements (D-,T-,JK- ?)
Develop a transition table
Develop boolean functions for  and 
Design circuitry at gate level
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VHDL ET062G & ET063G
Lecture 6
8
DESIGN OF STATE MACHINES
AUTOMATIC SYNTHESIS
Develop a state diagram for the problem
Write VHDL-code that captures the problem
Automatic synthesis will perform coding of
state graph and generate a gate level netlist
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VHDL ET062G & ET063G
Lecture 6
9
FINITE STATE MACHINES AND VHDL
COMPARISON
•
Medvedev is too inflexible
• Moore is preferred, because of safe
operation
• Mealy more flexible but danger of
•
•
Spikes
Unnecessary long paths (maximal clock
period)
MEDVEDEV MACHINE
Output IS the state
Two Processes
architecture RTL of MEDVEDEV is ... begin
REG: process (CLK, RESET)
begin
-- State Registers Inference
end process REG ;
CMB: process (X, STATE)
begin
-- Next State Logic
end process CMB ;
end RTL ;
Najeem Lawal, 2012
VHDL ET062G & ET063G
Lecture 6
One Process
architecture RTL of MEDVEDEV is ... begin
REG: process (CLK, RESET)
begin
-- State Registers Inference with Logic Block
end process REG ;
end RTL ;
11
MEDVEDEV EXAMPLE
architecture RTL of MEDVEDEV_TEST is
signal STATE,NEXTSTATE : STATE_TYPE ;
begin
Output IS the state
REG: process (CLK, RESET)
begin
if RESET=`1` then
STATE <= START ;
elsif CLK`event and CLK=`1` then
STATE <= NEXTSTATE ; end if ;
end process REG;
CMB: process (A,B,STATE)
begin
NEXTSTATE <= STATE ;
case STATE is
when START => if (A and B)=`0` then
NEXTSTATE <= MIDDLE ; end if ;
when MIDDLE => if (A and B)=`1` then
NEXTSTATE <= STOP ; end if ;
when STOP => if (A xor B)=`1` then
NEXTSTATE <= START ; end if ;
when others => NEXTSTATE <= START ;
end case ;
end process CMB ;
--concurrent signal assignments for output
(Y,Z) <= STATE ;
end RTL ;
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Lecture 6
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MEDVEDEV WAVEFORM
Output IS the state
•(Y,Z) = STATE => Medvedev machine
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Lecture 6
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MOORE MACHINE
Output is a function of ONLY the state
Three Processes
architecture RTL of MOORE is ...
begin
REG: -- Clocked Process
CMB: -- Combinational Process
OUTPUT: process (STATE)
begin -- Output Logic
end process OUTPUT ;
end RTL ;
Najeem Lawal, 2012
Two Processes
architecture RTL of MOORE is ... begin
REG: process (CLK, RESET) begin -- State
Registers Inference with Next State Logic
end process REG ;
OUTPUT: process (STATE)
begin -- Output Logic
end process OUTPUT ;
end RTL ;
VHDL ET062G & ET063G
Lecture 6
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MOORE MACHINE EXAMPLE
Output is a function of ONLY the state
architecture RTL of MOORE_TEST is
signal STATE,NEXTSTATE : STATE_TYPE ;
begin
REG: process (CLK, RESET)
begin
if RESET=`1` then
STATE <= START ;
elsif CLK`event and CLK=`1` then
STATE <= NEXTSTATE ;
end if ;
end process REG ;
CMB: process (A,B,STATE)
begin
NEXTSTATE <= STATE ;
case STATE is
when START => if (A and B)=`0` then
NEXTSTATE <= MIDDLE ; end if ;
when MIDDLE => if (A and B)=`1` then
NEXTSTATE <= STOP ; end if ;
when STOP => if (A xor B)=`1` then
NEXTSTATE <= START ; end if ;
when others => NEXTSTATE <= START ;
end case ;
end process CMB ;
-- concurrent signal assignments for output
Y <= ’1’ when STATE=MIDDLE else ‘0’ ;
Z <= ‘1’ when STATE=MIDDLE or STATE=STOP else ‘0’ ;
end RTL ;
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Lecture 6
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MOORE MACHINE WAREFORM
Output is a function of ONLY the state
•(Y,Z) changes synchronous with STATE => Moore machine
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Lecture 6
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MEALY MACHINE
Output is a function of state AND input
Three Processes
architecture RTL of MEALY is ...
begin
Two Processes
architecture RTL of MEALY is ...
begin
REG: -- Clocked Process
CMB: -- Combinational Process
MED: process (CLK, RESET) begin
-- State Registers Inference with Next State
Logic
end process MED ;
OUTPUT: process (STATE, X)
begin -- Output Logic
end process OUTPUT ;
end RTL ;
OUTPUT: process (STATE, X)
begin -- Output Logic
end process OUTPUT ;
end RTL ;
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Lecture 6
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MEALY MACHINE EXAMPLE
Output is a function of state AND input
architecture RTL of MEDVEDEV_TEST is
signal STATE,NEXTSTATE : STATE_TYPE ;
begin
REG: process (CLK, RESET)
begin
if RESET=`1` then
STATE <= START ;
elsif CLK`event and CLK=`1` then
STATE <= NEXTSTATE ;
end if ;
end process REG;
CMB: process (A,B,STATE)
Begin
-- Like Medvedev and Moore Examples
end process CMB ;
-- concurrent signal assignments for output
Y <= `1` when (STATE=MIDDLE and (A or B)=`0`) or
and B)=`0`) else `0` ;
(STATE=STOP and (A
Z <= `1` when (STATE=START and (A and B)=`1`) or (STATE=MIDDLE) or
(STATE=STOP and (A or B)=`1`) else `0` ;
end RTL ;
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Lecture 6
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MEALY MACHINE WAVEFORM
Output is a function of state AND input
•(Y,Z) changes with input => Mealy machine
•Notice the "spikes" of Y and Z in the waveform
•FSM has to be modeled carefully
so there are no spikes in normal operation.
Spike
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Lecture 6
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EXAMPLE OF STATE MACHINE IN VHDL
architecture rtl of fsm_simple is
type state_type is (start, r1, r2);
signal state : state_type;
begin -- rtl
update_state : process (clk, reset)
begin -- process fsm
if reset = '0' then
state <= start;
elsif clk'event and clk = '1' then
case state is
when start => if A = '0' then state <= start; else state <= r1; end if;
when r1
=> if A = '0' then state <= r1; else state <= r2; end if;
when r2
=> if A = '0' then state <= r2; else state <= start; end if;
end case;
end if;
A=0
end process update_state;
start
output_logic : process(state)
begin
case state is
when start => z <= '0';
when r1 => z <= '1';
when r2 => z <= '0';
end case;
end process output_logic;
end rtl;
A=1
z=0
r1
A=1
z=1
r2
z=0
A=1
A=0
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VHDL ET062G & ET063G
Lecture 6
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A=0
MEALY TYPE IN VHDL
aIn=0/yOut=0
architecture mealy of fsm2 is
type state is (S1, S2, S3, S4);
signal present_state, next_state: state;
begin
process (aIn, present_state) begin
CASE present_state IS
when s1 => if (aIn = ’1’)
then yOut <= ’0’; next_state <= s4;
else yOut <= ’1’; next_state <= s3;
end if;
when s2 => yOut <= ’1’; next_state <= s3;
when s3 => yOut <= ’1’; next_state <= s1;
when s4 => if (aIn = ’1’)
then yOut <= ’1’; next_state <= s2;
else yOut <= ’0’; next_state <= s1;
end if;
end case;
end process;
process begin
wail until clk = ’1’;
present_state <= next_state;
end process;
end mealy;
Najeem Lawal, 2012
VHDL ET062G & ET063G
Lecture 6
aIn=1/yOut=0
S1
aIn=-/
yOut=1
S4
aIn=0/
yOut=1
S3
aIn=1/yOut=1
S2
aIn=-/yOut=1
Output
function
yOut
aIn
next_state
present_state
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MOORE TYPE IN VHDL
library ieee; use ieee.std_logic_1164.all;
entity fsm1 is
port (aIn, clk: in std_logic; yOut: out std_logic);
end fsm1;
architecture moore of fsm1 is
type state is (s1, s2, s3, s4);
signal present_state, next_state: state;
begin
process (aIn, present_state) begin
case present_state is
when s1 => yOut <= ’0’;
if (aIn = ’1’) then next_state <= s1
else next_state <= s2;
when s2 => yOut <= ’0’;
if (aIn = ’0’) then next_state <= s3; end if;
when s3 => yOut <= ’1’;
if (aIn = ’0’) then next_state <= s4; end if;
when s4 => yOut <= ’1’;
if (aIn = ’0’) then next_state <= s1; end if;
end case;
end process;
process begin
wait until clk = ’1’;
present_state <= next_state;
end process;
end moore;
Najeem Lawal, 2012
VHDL ET062G & ET063G
Lecture 6
aIn=1
aIn=0
S1
yOut=0
S2
yOut=0
aIn=0
aIn=0
S4
yOut=1
S3
yOut=1
aIn=0
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COMPONENTS IN AN DIGITAL DESIGN
A digital design consists of
– At least one control unit (FSM)
– At least one datapath unit
• For example, adder, multiplier, comparator
• Register for temporary storage of variables
Often a design consists of many controllers and datapaths
Design model: FSM with datapath
– Describes the function of the designs containing both
control unit and datapath
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VHDL ET062G & ET063G
Lecture 6
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FSM WITH DATAPATH
Control
inputs
Control
unit
control
outputs
control
inputs
Data
inputs
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Data
inputs
Control signals
Datapath
Status signals
FSMD
VHDL ET062G & ET063G
Lecture 6
Data
outputs
control
outputs
Data
outputs
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DESIGN EXAMPLE
DESIGN A FUNCTION COMPUTING:
y  axb
Type
Description
#bits
D
in, data
values, positive integer, for a, x and b in sequence
8
start
in, control
Activate computation of Y, active high
1
busy
out, control
indicate that unit is busy computing
1
Y
out, data
The computed value Y
17
reset
in, control
Initialize the unit
1
clk
start
a=5
D
x=3
b = 10
busy
Y
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Y=25
VHDL ET062G & ET063G
Lecture 6
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CONT. DESIGN EXAMPLE
D
Y
start
busy
Y = a·x + b
reset
clk
External control signals
Controlling the unit
External data signals
reset
start
internal control signals
D
storeA
Control unit
storePr
Datapath
External control
signal
Y
busy
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VHDL ET062G & ET063G
Lecture 6
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CONT. DESIGN EXAMPLE
D
Start=0
start
busy = 0
storeA = 0
storePr = 0
clk
storeA
EN
X
Start=1
getA
multAX
addB
busy = 1
storeA = 1
storePr = 0
busy = 1
storeA = 0
storePr = 1
busy = 1
storeA = 0
storePr = 0
A
×
clk
storePr
EN
B
A×X
+
A×X+B
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VHDL ET062G & ET063G
Lecture 6
Y
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SUMMARY
ALL DIGITAL DESIGNS FOLLOW THE MODEL OF FSMD
DESIGN FLOW
– Specify the algorithm to be implemented
– Identify
• Which components are needed in the datapath
• Which states are needed in the control unit
• Which control signals are needed to the datapath
• Which status signals are needed to the control unit
– Develop
• State Transition Graph for the control unit
• Block diagram for the data path
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VHDL ET062G & ET063G
Lecture 6
28
QUESTIONS
ABOUT FPGA / VHDL
ABOUT VGA DISPLAY / TIMING
ABOUT IMAGE SENSOR TIMING
ABOUT RANGE SENSOR
ABOUT LINE BUFFERS
ABOUT MEMORIES & COUNTERS
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VHDL ET062G & ET063G
Lecture 5
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END OF LECTURE 6
OUTLINE
– Range Sensor display
– FSM in VHDL
• Medvedev FSM
• Moore FSM
• Mealy FSM
– FSMD – FSM and Data path
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Lecture 5
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TESTBENCH IMAGES
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Lecture 5
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RANGE SENSOR
SRF05 HTTP://WWW.ROBOTSTOREHK.COM/SENSORS/DOC/SRF05TECH.PDF
– 10us pulse to the Trigger input
– 50ms period between each Trigger pulse
– Mode 1 recommended
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VHDL ET062G & ET063G
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PROJECT IMPLEMENTATION
CONTROLLER IS FPGA
– System Clock and
Exposure are generated
– Understand timing
diagrams and implement
the project.
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SLIDING WINDOW
– An image is read from left to
right and top to bottom
• sliding
column
row
– Given an algorithm with many
tasks
O(x,y) = F(x,y) x I(x,y)
in
A)
– Some of the task are
neighbourhood oriented
• sliding window
• N x M sliding window.
• N and M are odd numbers
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VHDL ET062G & ET063G
p1
p2
p5
p3
p6
p4
p7
Sliding window
B)
Task
Image filter
34
out
SLIDING WINDOW
Neighbourhood p11 p12 p13
data
p21 p22 p23
p31 p32 p33
a)
b)
Linebuffers
In
data
...
Suggested implementation
architecture
1. linebuffers
2. Boundary controller
3. Pixel switch
4. Filter function
5. Output synchronisation
SLWC
Window
ctrl
Neighbourhood
output
(2a)
p11 p12 p13
p21 p22 p23
p31 p32 p33
Line buffer
d
p33
VHDL ET062G & ET063G
Sync.
Pixel
switch
(2b)
dpixel
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Image filter
function
Out
data
Line buffer
d
p32
d
p31
p23
35
d
d
p22
p21
p13
d
p12
p11
SLIDING WINDOW
W
ω
I
width
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VHDL ET062G & ET063G
36
height
– At the image edges
– There are invalid pixel
– How do you build a valid
neighbouthood of pixels around edge
pixels?
– 3 alternatives
• Avoid processing edge pixels
• Copy centre pixel to the invalid
pixel locations
• Reflections. Default to 0 or 255