Transcript Diskreetne Matemaatika. S.

IAY 0600
Digital Systems Design
Digitaalsüsteemide disain
Course Overview
Alexander Sudnitson
Tallinn University of Technology
Administrative
Aleksander Sudnitsõn (Alexander Sudnitson)
Department of Computer Engineering
(Arvutitehnika instituut)
Associate Professor (dotsent)
ICT-503
[email protected]
Tel. +372 5092356
www.pld.ttu.ee/~alsu
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Lectures
Lecture:
Thursday 14.00 - 15.30
http://ati.ttu.ee/~alsu/IAY0600.html
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Course resources
www.pld.ttu.ee/~alsu
IAY0600 Digitaalsüsteemide disain (ERIKURSUS)
Digital Systems Design
IAY0600 Digitaalsüsteemide disain (PRAKTIKUM)
Digital Systems Design (LABS)
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Course goals
 to elaborate knowledge of the design process
from design description in VHDL through
functional simulation, synthesis, timing
simulation, and PLD (FPGA) programming;
 to gain experience in designing and verifying
digital systems using synthesis and simulation
tools;
 to provide students the theory and practice of
rapid prototyping of digital systems in a
laboratory environment;
 to provide students an understanding of
specifying, designing and analyzing of
asynchronous systems.
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Outcomes
to proceed from a digital system description in
VHDL to its implementation in a PLD (FPGA) using of
a number of computer-aided design software tools;
to understand how to interpret design tool outputs
in evaluating alternative system designs for a specific
set of requirements, and how to use the knowledge
gained to improve the design;
to understand and comprehend asynchronous
design methods, computational models, design
terminology.
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Main topics
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The course is based on the development of a
real-world projects and case studies
Synthesizable VHDL
Digital systems design methodology using
VHDL and PLD (FPGA)
FPGAs as means for building reconfigurable
systems
Rapid prototyping of digital systems.
Principles of asynchronous design (a systems
perspective).
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Grading
To stimulate the student’s activity an
project-based evaluation approach is
adopted. Grading consists of control of
knowledges in examinations (weighted 40%
in final grade) and of the demonstration of
the projects and the quality of a written
report (weighted 60% in final grade).
“LEARNING BY DOING”
Learning By Example Using VHDL
(with FPGA Evaluation Boards)
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Labs
Thursday 16.00 - 17.30 (19.15)
Assistant_1 Dimitri Mihhajlov
Assistant_2 Muhammad Adeel Tajammul
Every completed experiment (project) must be
presented to Assistant_1 (D. Mihhailov), who
will evaluate student’s results and effort
http://ati.ttu.ee/~alsu/IAY0600l.html
IAY0600l
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Compulsory Labs
Tutorial (lab) is optional
(2) Comparator
(3) Adder
(4) Parameterizable Adder
(5) Finite-State Machine
(6) Low-Power Design
Normally this
labs should
be done by
13th week
(7) Least Common Multiple
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Invited Labs
(8)Invited Lab (7.05.2015 & 14.05.2015)
Nominal deadline for Invited Labs is
16th week (21.05.2015)
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Optional Labs
(8) Creeping Line
Optional Lab 9 gives additional 20% to the
final grade
Altera FPGA-based
(2) VGA Port and PS/2 Mouse Port
(3) IR Remote Control and LCD Display
Any optional Altere FPGA-based Lab (or both)
gives additional 20% to the final grade
Nominal deadline for optional Labs is
16th week (21.05.2015)
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Labs
The laboratory assignments are done using the
Xilinx ISE Software (VIVADO design suite in
invited labs).
Educational boards related to this course:
Nexys 3
ZedBoard (invited Labs)
Altera (optional Lab)
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CAD environment
The design suites support all steps of the FPGA
design flow (design entry, simulation, synthesis,
translation and device configuration). Both may be
freely downloaded by students, which permits to
continue working on projects outside university
Xilinx, Inc., ISE Design Suite, available at:
http://www.xilinx.com/products/design-tools/isedesign-suite/
Altera, Corp., Design Software, Quartus II, available
at: http://www.altera.com/products/software/sfwindex.jsp
Xilinx Inc., Vivado Design Suite, available at:
http://www.xilinx.com/products/design-tools/vivado/
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Slides
http://ati.ttu.ee/~alsu/IAY0600.html
Lecture slides (to be published before
each lecture).
Auxiliary material
Digital Systems Modeling and Synthesis
http://www.ati.ttu.ee/IAY0340/schedule.html
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Textbooks
Lecture slides (to be published before each lecture).
Skljarov V., Skliarova I., Sudnitson A. Design of
FPGA-based Circuits using Hierarchical Finite State
Machines. TUT Press, Tallinn, 2012, 240 p.
Short K. L. VHDL for Engineers, Pearson Education,
Inc., 2009, 2013.
Chu P.P. FPGA Prototyping Using VHDL Examples:
Xilinx Spartan-3 Version, Jonh, Willey & Sons, 2008.
Hamblen J. O, Hall T.S., and Furman M. D. Rapid
Prototyping of Digital Systems, Springer, 2007.
Sparso J. and Furber S. Principles of Asynchronous
Circuit Design: a Systems Perspective. Boston:
Kluwer, 2001.
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Publications
1. V. Sklyarov, I. Skliarova, A. Sudnitson, M. Kruus, “Teaching FPGAbased Systems,” 2014 IEEE Global Engineering Education Conference
(EDUCON), IEEE, Istanbul, Turkey, Apr. 2-5, 2014, pp. 460-469.
2. Sklyarov, V.; Skliarova, I.; Kruus, M., Sudnitson, A. “Using Mobile
Technology to Enhance Teaching Reconfigurable Systems,” IEEE
International Conference on Teaching, Assessment and Learning for
Engineering 2013 (IEEE TALE 2013), IEEE, Kuta, Indonesia, August
26-29, 2013, pp. 478-483.
3. V. Sklyarov, I. Skliarova, A. Sudnitson, “Methodology and International
Collaboration in Teaching Reconfigurable Systems,” 2012 IEEE Global
Engineering Education Conference (EDUCON), IEEE, Marrakesh,
Morocco, Apr. 17-20, 2012, pp. 1143-1152.
4. A.Sudnitson, D.Mihhailov, M.Kruus, “Project-Oriented Approach to LowPower Topics in Advanced Digital Design Course,” Electronics and
Electrical Engineering, 2010, No. 6(102), pp. 151-154.
5. A.Sudnitson, D.Mihhailov, M.Kruus, “Cooperation of FPGA-Based
Educational Boards and Web-Based Point Design Tools for Research
and Education,” IFIP EduTech’09 International Workshop,
Florianopolis, Brazil, Oct.15-16, 2009, 13p.
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Digital System
A discrete system is a system in which signals have a finite number
of discrete values.
(This contrasts with analog systems, in which signals have values
from an infinite set).
Inputs
Discrete
System
Outputs
Any finite number of discrete values can be represented by a vector
of signals with just two values. Such a signal, which takes only two
values, is called a digital signal (or binary, or logic), and any device
that processes digital signals is called a digital device.
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Design process
The design process consists of obtaining an implementation that
satisfies the specification of a system.
Specification
(behaviour)
Analysis (verification)
Synthesis
Implementation
(structure)
The analysis of a system has an objective the determination of its
specification from an implementation.
The synthesis consists of obtaining an implementation that satisfies
the specification of a system
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Design representation
Three different domains of description:
A behavioral or functional representation is one that looks at the
design as a black box. A behavioral representation describes the
functionality but not the implementation of a given design, defining
the black box’s response to any combination of input values.
A structural representation is one that the black box as a set of
components and their connections. It specifies the product’s
implementation without explicit reference to its functionality.
The functionality could be derived from that of its interconnected
components.
A physical representation is one that specifies the physical
characteristics of the black box, providing the dimensions and
locations of each component and connection contained in the
structural description..
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Modified Y Chart: levels of abstruction
Behavior
Description
Structural
Description
System
Abstract
Processes
Programmable
cores, IPs, ASICs
Architectural
Algorithm
Dataflow
Processor, Memory,
Peripheral interface
Register Transfer
(RTL)
Registers, Adders,
Multipliers, etc.
Logic
Boolean equations
Logic netlist,
Schematic
View
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Timing units at different levels
Behavior
Description
Structural
Description
Time Units
Comuncation Transaction
Abstract
Processes
Algorithm
Computation Step
Dataflow
Boolean equations
Clock Cycle
Delay
Programmable
cores, IPs, ASICs
Processor, Memory,
Peripheral interface
Registers, Adders,
Multipliers, etc.
Logic netlist,
Schematic
View
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Modified Y Chart : this course area
Synthesis
Behavior
Description
Analysis
Structural
Description
Algorithm
Processor, Memory,
Peripheral interface
Dataflow / RTL
Registers, Adders,
Multipliers, etc.
Boolean equations
Logic netlist,
Schematic
View
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Modified Y Chart: transformations
Behavior
Description
Algorithm
Structural
Description
Algorithmic
Register-Transfer
Dataflow
Boolean equotions
Transformations
Processor, Memory,
Peripheral interface
Registers, Adders,
Multipliers, etc.
Logic
Logic netlist,
Schematic
View
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Chart supporting synthesis activity
Behavior
Description
Structural
Description
Algorithmic level
of abstraction
Behavioral
synthesis
Register-transfer
level of abstraction
RTL
synthesis
Logic level of
abstraction
Logic
synthesis
View
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Example: HalfAdder
Behavior
a b
Structure
Sum Carry
0 0
0
0
0 1
1
0
1 0
1
0
1 1
0
1
a
b
a
Sum = ¬a&b  a&¬b
=ab
b
Sum
HalfAdder
Carry

Sum
&
Carry
Carry = a & b
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Example: HalfAdder Behavioral Description
a
b
Sum
Sum = ¬a&b  a&¬b
=ab
Carry
Carry = a & b
HalfAdder
entity HALFADDER is
port(a, b: in bit; Sum, Carry: out BIT);
end HALFADDER;
architecture RTL of HALFADDER is
begin
Sum <= a xor b;
Carry <= a and b;
end RTL;
This is data flow behavioral description
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Brief History of VHDL
VHDL is an industry standard hardware description
language that is widely used for specifying,
modeling, designing, an simulating digital systems.
VHDL is an acronym for VHSIC (Very High Speed
Integrated Circuit) Hardware Description Language.
The first version of VHDL:
IEEE-1076 1987
The most commonly supported by CAD
tools version of VHDL:
IEEE-1076 1993
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VHDL for Synthesis (vs. for Simulation)
VHDL was originally developed as a language for
describing digital systems for the purpose of
documentation and simulation, but not for synthesis.
In 1999, the IEEE issued IEEE Std 1076.6-1999,
IEEE Standard for VHDL Register Transfer Level
(RTL) Synthesis. This standard described a subset of
IEEE Std 1076 suitable for RTL synthesis. It also
described the syntax and semantics of this subset
with regard to synthesis.
IEEE 1076.6 defines a subset of the language that is
considered the official synthesis subset.
A revision of this standard was issued in 2004 and
2008.
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VHDL vs. Verilog
Government Developed
Ada based
Commercially
Developed
C based
Strongly Type Cast
Mildly Type Cast
Difficult to learn
Easier to Learn
More Powerful
Less Powerful
Features of VHDL and Verilog:
technology/vendor independent
portable
reusable
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VHDL for specification, simulation, and synthesis
VHDL for Specification
VHDL for Simulation
VHDL for Synthesis
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Design flow for VHDL/PLD methodology
In our course
PLD = FPGA
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