Transcript Automating Thermo-Mechanical Warpage Estimation of PCBs

Automating Thermo-Mechanical
Warpage Estimation of PCBs/PCAs
Using a Design-Analysis
Integration Framework
Presenter: Russell Peak
Authors:
Manas Bajaj (Georgia Tech), Russell Peak (Georgia Tech),
Dirk Zwemer (AkroMetrix), Thomas Thurman (Rockwell Collins),
Lothar Klein (LKSoft), Giedrius Liutkus (LKSoft), Kevin Brady (NIST),
John Messina (NIST), Mike Dickerson (InterCAX)
v3 - 2006-07-07
http://eislab.gatech.edu/pubs/conferences/2006-user2user-bajaj/
Abstract
Accurate prediction, validation and reduction of thermally-induced PCB warpage are critical for
enhancing manufacturing yield and reliability in time-to-market driven electronics product
realization.
In this paper, we describe a methodology to simulate thermally-induced warpage of PCBs and
PCAs. We will demonstrate this analysis methodology using the following path: read ECAD
designs from Mentor Graphics Board Station, identify features relevant to warpage analysis,
create idealized analysis models, select solution technique and create solver-specific models (e.g.
ANSYS and ABAQUS models for finite-element solution), identify warpage hotspots and
calculate metrics to assist PCB/A designers in reducing warpage. We shall also present initial
results from experimental verification of this technique using a shadow moiré (TherMoiré®)
method.
This methodology provides highly automated simulation capabilities using analysis concepts,
idealizations, and solution techniques for modularized and configurable simulation studies. It
leverages open standards including ISO 10303 (STEP AP210 – www.ap210.org and Standard Data
Access Interface - see www.jsdai.net).
Resources: (a) http://www.InterCAX.com/warpage
(b) http://eislab.gatech.edu/projects/nist-warpage/
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MB,RP et al., PWB/PWA Warpage, May 2006
Contents

Warpage Context
Definition and impact
— PCB/A features affecting warpage
— Requirements for warpage analysis
—

Sample simulation results and validation
Bare boards (PCBs)
— Assembled boards & chip pkgs. (PCAs, BGAs)
—

Methodology and tools
Multi-representation architecture
— Tool availability
—

Summary
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MB,RP et al., PWB/PWA Warpage, May 2006
Doc/Proc/Reg
Guidelines
Layout
Functional
Part Symbol
& Footprint Placement
Design
Requirements
Electronics Product Realization
Routing
Learn today
Utilize tomorrow
Review
Corrections
Release
Environmental
Build
Fabricate
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MB,RP et al., PWB/PWA Warpage, May 2006
Assemble
Test/Inspect
Warpage - Definition

WARPAGE is out of plane deformation of the
artifact, caused by differential (non-homogenous)
shrinkage or expansion of elements composing
the artifact.
Out of plane deformation of
a linear element
Warpage of 2D artifacts
( basic modes)
Saddle Deformation
Basic Model
 = (b L2 T) / t where
L: Undeformed Length; t: Undeformed
Thickness; T: Temperature Change; b:
Specific Coefficient of Thermal Bending
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MB,RP et al., PWB/PWA Warpage, May 2006
Bowl Deformation
PCA/B Warpage - Illustration
Undeformed Shape
Deformed Shape
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Warpage – Impact and Requirements
Ref: Thinking Globally, Measuring Locally
Editorial by Patrick Hassell, AkroMetrix
Impact
 Low manufacturing yield and high rework
of interconnects
Lack of co-planarity of component footprints
— Fine pitch technology
— Low solder paste volume
—
Requirements
 Managing warpage requirements
Enforce local warpage requirements
— Relax global warpage requirements
—
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MB,RP et al., PWB/PWA Warpage, May 2006
Warpage Effects
[after Ding, 2003; Zwemer, 2006; et al.]
Estimated Impact: $100M / year
Factors
—
—
—
—
—
—
—
Consequences
CTE mismatch: global & local
Temperature / humidity variation
Temperature / humidity gradient
Material rigidity
Thermal conductivity
Geometric size & aspect ratio
Component layout
Underfill
Molding
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Vias
Solder Balls
PWB
—
—
—
—
—
—
Misregistration
Solder opens
Solder shorts
Delamination
Solder fatigue
Die cracking
Die/Chip
BGA Substrate
Contents

Warpage Context
Definition and impact
— PCB/A features affecting warpage
— Requirements for warpage analysis
—

Sample simulation results and validation
Bare boards (PCBs)
— Assembled boards & chip pkgs. (PCAs, BGAs)
—

Methodology and tools
Multi-representation architecture
— Tool availability
—

Summary
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Complex Features Affecting
Thermo-Mechanical Behavior
PCB Layout
PCB Level
Features on PCB - Notional Figure
Footprint occurrence
Via
Traces
Complete
trace curve
not shown
Stackup
Land
PCB outline
M150P2P11184
M150P1P21184
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Plated through
hole
Mechanical (tooling / drilling)
hole
Complex Features Affecting
Thermo-Mechanical Behavior
PCA Level: Complex Components
Isometric View
Side View
Mold Resin
Si Chip
Die Attach
Solder Resist
Cu Foil
BT-Resin Core
Cu Foil
BT-Resin Core
Cu Foil
BT-Resin Core
Cu Foil
Solder Resist
Solder Balls (Diagonal Grid Pattern)
Photo: www.shinko.co.jp
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Contents

Warpage Context
Definition and impact
— PCB/A features affecting warpage
— Requirements for warpage analysis
—

Sample simulation results and validation
Bare boards (PCBs)
— Assembled boards & chip pkgs. (PCAs, BGAs)
—

Methodology and tools
Multi-representation architecture
— Tool availability
—

Summary
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Requirements for Warpage Analysis



Availability of a rich product model
— ECAD design details
— PCB layer stackup details
— Material behavior and properties
Analysis model creation capabilities
— Idealized PCB/A features
— Boundary conditions
— Thermal loading
FEA model creation and solution capabilities
— FE mesher
— FE solver
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Rich Product Model
http://eislab.gatech.edu/pubs/journals/2004-jcise-peak/
Traditional
Tools
Electrical
CAD Tools
Mechanical
CAD Tools
Systems Engineering
Tools
Eagle
Pro/E
Doors
Mentor
Graphics
AP210
…
Teamcenter
Requirements
NX
AP203, AP214
AP233, SysML
Collective Product Model
Standards-based
Submodels
AP210
Gap-Filling
Tools
XaiTools
XaiTools
PWA-B
PWA-B
AP2xx
pgef
PWB Stackup Tool, Engineering
…
Framework Tool
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Building Blocks:
• Information models & meta-models:
• International standards
• Industry specs
• Corporate standards
• Local customizations
• Modeling technologies:
• Express, XML, UML, OWL, …
EPM,
LKSoft,
LKSoft,
…
Theorem, …
STEP-Book AP210,
SDAI-Edit,...
Instance Browser/Editor
STEP AP210 (ISO 10303-210)
Domain: Electronics Design
R
~1200 standardized concepts (many applicable to other domains)
Development investment: O(100 man-years) over 10+ years
Configuration Controlled Design of Electronic Assemblies,
their Interconnection and Packaging
Interconnect
Assembly
Printed Circuit Assemblies
(PCAs/PWAs)
Product Enclosure
Die/Chip
Packaged Part
Printed Circuit
Substrate (PCBs/PWBs)
Die/Chip
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et al., -PWB/PWA
Warpage,
May 2006
2003-04
Adapted from
2002-04 version
by Tom Thurman, Rockwell-Collins
Package
External Interfaces
STEP AP210 (ISO 10303-210)
http://www.ap210.org
Used for warpage analysis
Scope
Functional Models
Requirements Models
• Functional Unit
• Interface Declaration
• Network Listing
• Simulation Models
• Signals
• Test Bench
•
•
•
•
Rules Models
• Design
• Manufacturing
•…
Assembly Models
•
•
•
•
•
User View
Design View
Component Placement
Material Product
Complex Assemblies with
Multiple Interconnects
Design Control
• Geometric Dimensioning
and Tolerancing
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Design
Constraints
Interface
Allocation
Component / Part Models
• Analysis Support
• Package
• Material Product
• Properties
• “White Box”/ “Black Box”
• Test Bench
•
•
•
•
•
•
•
•
•
•
Configuration Mgmt
Identification
Authority
Effectivity
Control
Net Change
•
•
•
•
Interconnect Models
Usage View & Design View
Bare Board Design
Layout Templates
Layers and Layer
Technologies
Stackup
Geometric Models
2D
3D
CSG, Brep…
EDIF, IPC, GDSII
compatible “trace” model
Example Design in STEP Book AP210 Pro
(PCB Layout View)
Originating ECAD Model from:
Mentor Board Station
Current Tool:
STEP Book AP210 v2.3
Current Model based on:
STEP AP210
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Example Design in
XaiTools PWA-B 2.0.b1 Stackup Editor
Originating ECAD from:
Mentor Board Station
Current Tool:
XaiTools PWA-B v2.0.b1
Current Model based on:
STEP AP210
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PCB Warpage Analysis Model Creation
Context
Building Block-based Analysis Model
Single Layer View
length
width
AP210-based
Manufacturing
Product Model
…
Top view of “effective” grid
elements in top layer of the PCB
Effective Material
Property
Computation
…
thickness
Side view of the PCB with
“effective” grid elements across
the stratums
Given:
Context Attributes
Grid (Sieve) • Thermal loading profile
Size
• Boundary Conditions (mostly displacement)
• Idealize PWB stackup as a layered shell
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• Thermal loading profile
• Boundary Conditions (mostly displacement)
• Idealize PWB stackup as a layered shell
Contents

Warpage Context
Definition and impact
— PCB/A features affecting warpage
— Requirements for warpage analysis
—

Sample simulation results and validation
Bare boards (PCBs)
— Assembled boards & chip pkgs. (PCAs, BGAs)
—

Methodology and tools
Multi-representation architecture
— Tool availability
—

Summary
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Chopped PCB Regions for Analysis
in XaiTools PWA-B 2.0.b1
First (Top) Design Layer
Second (Bottom) Design Layer
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Example Design - Coeff. of Thermal
Bending Results in XaiTools PWA-B 2.0
Regions with
greatest
mismatch
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Example Design – Finite Element Model Creation
and Solution Input to ANSYS
ANSYS APDL-based
description for creating and
solving the finite-element
model
XaiTools PWA-B 2.0.b1
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Example Design – FEA Warpage Results
Out-of-plane deformation
Conditions
T = 125 deg. C - uniform
heating from 25 deg. C to
150 deg. C
Y-min and Y-max edges are fully
constrained
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Overall Process - Circuit Board Stackup Design &
Warpage Analysis Using AP210 (WIP)
GIT and NIST EEEL in collaboration with AkroMetrix, InterCAX/LKSoft, and Rockwell Collins
width
length
…
ECAD and STEP AP210-based
Product Model
Design Improvement
Feedback
Analysis Building Block Model
(idealized bodies with effective material properties)
PCB Warpage Profile
(given: thermal profile +
boundary conditions)
CTB Map
(smeared property to
identify material
distribution)
http://eislab.gatech.edu/projects/
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thickness
Identification of warpage “hotspots” on a PCB
PCB Warpage: Validation Results
http://eislab.gatech.edu/pubs/conferences/2004-eurosime-zwemer/
Simulation Results
Physical Measurements in
TherMoiré oven chamber
www.AkroMetrix.com
Measurement Results
SMM - FEA Mesh Model
200
25
100
50
0
-50
Scale (mils)
Temperature (C)
150
0C
20
15
10
5
26
-100
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MB,RP et al., PWB/PWA Warpage, MayModel
2006 Exp't
BoardStation “Module 10” Example in SB210 Pro v2.3
9 layer board
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Module 10: Idealization Grids
for Effective Material Properties
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Module 10: CTB Maps
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Module 10: FEA Warpage Results
out-of-plane deformation (Uz) in inches
delta T = 150 C
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Recent Production Test Cases
Test Case Name
CAD Source
Design - 05
Design - 07
Design - 002J BOT
Design - 002J MOD
Design - 002J TOP
Cable DB
Surface Mount Flasher
Zuken Visula
Zuken Visula
Zuken Visula
Zuken Visula
Zuken Visula
Mentor Board Station
Mentor Board Station
—- Need more Mentor designs for testing —
(collaboration opportunity!)
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MB,RP et al., PWB/PWA Warpage, May 2006
AP210 File
Size
No. of Layers
Conductive
Total
(MB)
119.3
39.4
18.9
100.6
29.5
1.0
0.5
9
10
1
12
1
2
2
No. of
Components
(approx.)
23
22
1
25
1
5
5
619
559
1012
1757
745
80
12
PCA viewed in STEP Book AP210 Pro
Design-07
559 components
10 circuit layers
Source ECAD Tool: Zuken Visula
Co-efficient of Thermal Bending (per deg C)
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MB,RP et al., PWB/PWA Warpage, May 2006
Warpage Profile (z-axis deflection) – 25C to 150 C
Design –
02MOD
PCA viewed in STEP Book AP210 Pro
1757 components
12 circuit layers
Source ECAD Tool: Zuken Visula
Co-efficient of Thermal Bending (per deg C)
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Warpage Profile (z-axis deflection) – 25C to 150 C
Contents

Warpage Context
Definition and impact
— PCB/A features affecting warpage
— Requirements for warpage analysis
—

Sample simulation results and validation
Bare boards (PCBs)
— Assembled boards & chip pkgs. (PCAs, BGAs)
—

Methodology and tools
Multi-representation architecture
— Tool availability
—

Summary
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PCA Warpage
Automated Analysis Model Creation
cross-section view
c1. component designs / libraries
(e.g., chip packages like
plastic ball grid arrays (PBGAs) )
i
c2. Idealized component designs (APMs)
and simulation templates (CBAMs) APM ABB
APM ABB
ECAD layout view
ABBSMM
idealization preparation view
b2. Idealized PCB design (APM)
and simulation template (CBAM)
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MB,RP et al., PWB/PWA Warpage, May 2006
PCB = printed circuit board (bare board)
analytical assembly view
c3. Analytical system models (ABBs)
(~400 analytical bodies per component)
Idealized components
d1. Combined
analytical system model
(~1000+ analytical bodies)
side view
Idealized PCA
i
a1. PCA design
plus b1. PCB design
exploded view
APM ABB
b3. Analytical system model (ABBs)
(~50 analytical multi-layer shell bodies)
Idealized PCB
PCA = printed circuit assembly = PCB + components, etc.
e1. Combined FEA mesh model (SMM)
(~50K elements avg. per complex component)
Case 1:
1 PBGA 265 on top
Automated PCA design
warpage analysis
U3
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Case 2:
2 PBGA 265s on top
U3
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MB,RP et al., PWB/PWA Warpage, May 2006
Case 3:
3 PBGA 265s on top
Qualitative comparison
- Different board & components
(somewhat similar)
- Good warpage shape results
comparison
- Similar total warpage results
(2.2 mils vs. 1.7 mils = ~23% delta)
[Ding, 2004] results
InterCAX results
XaiTools Electronics
(SBIR Phase 1 prototype)
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MB,RP et al., PWB/PWA Warpage, May 2006
Total Warpage for T=150C: = 0.0022 in
[scaled from 0.07 mm @ T=183C]
Total Warpage for T=150C: 0.0017 in
Case 4: PCA with top & bottom PBGAs
Analytical model in IDA-STEP as imported from AP203
Produced by idealizing AP210-based PCB design (from ECAD tool)
and combining with idealized chip package models in XaiTools Electronics prototype (XE), and exporting as AP203
Bare PCB
Two PBGA 265
(top side)
One PBGA 441
(bottom side)
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Dense off-pitch
body
interactions
(challenging for
FEA meshers)
Case 4: PCA with top & bottom PBGAs
Mesh model in Abaqus as imported from native Abaqus format
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[xx - view needs update]
Case 4: PCA with top & bottom PBGAs
FEA mesh model in Abaqus (cont.)
Mesh in dense chip package solder ball regions
Auto-generated mesh between chip package substrate layers,
solder balls, and PCB layers
[xx - view needs update]
(same region in full wireframe view)
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MB,RP et al., PWB/PWA Warpage, May 2006
Case 4: PCA with top & bottom PBGAs
Solved FEA model in Abaqus
PCA top
Warpage
(u3 = out-of-plane deformation)
Preliminary Warpage Results
(to be further validated in Phase 2)
Results - Case 4:
- Demonstrated FEA meshing feasibility (main challenge)
- Good results, trends, and compatibility
with similar cases [Ding, 2004; Powell, 2006]
- Results reveal anticipated asymmetric effects
- High fidelity PCB model considers
local feature density differences
- Future work will try more effective idealizations (ex. shells)
& correlate with physical measurements
PCA bottom
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MB,RP et al., PWB/PWA Warpage, May 2006
Bare board (PCB) warpage
Case 5: PBGA Chip Package on Sample PCB
Deformation magnitude results: PCA 6230 (w/ PBGA 441)
Known Results [Zeng, 2004; Shinko]
InterCAX SBIR Phase 1 Results
inches mm
0.00161
0.00150
0.00100
0.00050
[after Zeng, 2004]
vc6230 pbga 441 — delta T = 70 C
XCP + Patran pre-processing
Abaqus solving and Patran post-processing
0.00000
XE + Simmetrix pre-processing
Abaqus solving and post-processing
Phase 1 Results - Case 5
- Excellent comparison of deformation pattern
- Very good comparison of max. warpage values (1.61 mils vs. 1.50 mils = ~7% delta)
- Possible deviation causes: different meshing approach, different solver version, etc.
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PCA Warpage Capabilities
NIST SBIR FY05 Program  InterCAX Phase 1 Project  July, 2005 -January, 2006
http://www.InterCAX.com/warpage/

Main Phase 1 results
—
—
—
—
—

Successfully demonstrated feasibility of auto-generating
complex FEA models from AP210-based ECAD designs
Included localized board properties key for warpage prediction
Achieved good correlation with published results (within 7%)
Reduced simulation time by 80% for benchmark case
Automatically simulated design configurations ~5 times larger
than previously practical
Excellent outlook for next steps
—
—
Phase 2
Services and tools for industry
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MB,RP et al., PWB/PWA Warpage, May 2006
Contents

Warpage Context
Definition and impact
— PCB/A features affecting warpage
— Requirements for warpage analysis
—

Sample simulation results and validation
Bare boards (PCBs)
— Assembled boards & chip pkgs. (PCAs, BGAs)
—

Methodology and tools
Multi-representation architecture
— Tool availability
—

Summary
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MB,RP et al., PWB/PWA Warpage, May 2006
Multi-Representation Architecture (MRA) for
Design Analysis Integration
Tree View
Bare PWB
Electrical
Mechanical
Warpage
Manufacturing
Product Model
Manufacturability
Analysis
Product Model
PTH Fatigue
Context-Based
Analysis Model
Layered Shell
Effective Materials Properties
Analysis
Building Blocks
Finite Element
Solution
Method Model
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MB,RP et al., PWB/PWA Warpage, May 2006
Multi-Representation Architecture (MRA) for
Design Analysis Integration
Stepping-Stone Model View
ECAD Tools and
Manufacturable Product Model
(STEP AP210-based)
Analyzable
Product Model
Context-Based Analysis Model
APM
Analysis Building Block
Printed Wiring Assembly (PWA)
Solution Method Model
CBAM
APM
Component
Solder
Joint
ABB
SMM
ABB
Component
Solder Joint
PWB
T0
ABBSMM
body1
body4
body3
body2
Printed Wiring Board (PWB)
Solution Tools
(ANSYS, ABAQUS …)
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MB,RP et al., PWB/PWA Warpage, May 2006
MRA-based Model Browser
Design Artifacts – PCA, PCB,
Components, etc.
Design Libraries
Product-specific Analysis Models
Reusable Analysis Models
Solution Models and
Results – Finite Element
Model, etc.
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MB,RP et al., PWB/PWA Warpage, May 2006
Tool Availability

STEP Book AP210 Pro v2.3
—
—

XaiTools PWA-B v2.0
—
—

Imports & views Mentor Graphics designs:
BoardStation (Expedition under development)
Enables enrichment & AP210 output
Stackup editor
Bare board warpage analysis
XaiTools Electronics v1.0 (prototype)
—
Assembled board warpage analysis
Product & Service Information:
http://www.InterCAX.com/warpage/
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Collaboration Opportunities

Test cases

Georgia Tech research project
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MB,RP et al., PWB/PWA Warpage, May 2006
Contents

Warpage Context
Definition and impact
— PCB/A features affecting warpage
— Requirements for warpage analysis
—

Sample simulation results and validation
Bare boards (PCBs)
— Assembled boards & chip pkgs. (PCAs, BGAs)
—

Methodology and tools
Multi-representation architecture
— Tool availability
—

Summary
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MB,RP et al., PWB/PWA Warpage, May 2006
Summary

Automated board warpage analysis
—
—

Bare board stackup design and warpage analysis
Assembled board warpage analysis
Use of rich product models
to drive high-fidelity analyses
—
AP210 interface to Mentor Graphics ECAD tools

Commercial tools and services

Collaboration opportunities
—
—
Georgia Tech research project
Test cases
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MB,RP et al., PWB/PWA Warpage, May 2006
References

InterCAX warpage resources
—

Georgia Tech-NIST project for bare board warpage simulation
—



http://www.InterCAX.com/warpage/
http://eislab.gatech.edu/projects/nist-warpage/
Hai Ding (2004) Prediction and Validation of Thermomechanical
Reliability in Electronic Packaging. Doctoral Dissertation,
Georgia Institute of Technology, Atlanta.
Reinhard Powell (2006) Development of FE Prediction Tools and
Convective Solder Reflow Projection Moiré Warpage Measurement
System. Doctoral Dissertation, Georgia Institute of Technology, Atlanta.
Sai Zeng (2004) Knowledge-based FEA Modeling for Highly Coupled
Variable Topology Multi-body Problems. Doctoral Dissertation,
Georgia Institute of Technology, Atlanta.
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NIST Disclaimer
This document may identify commercial
product names and materials by other parties
to describe certain procedures or to provide
concrete examples (i.e., to help clarify
abstract concepts via specific instances). In
no case does product or material
identification imply recommendation or
endorsement by the authors or their
organizations, nor does it imply that such
items are necessarily the best available for
the purpose. Company, product, or service
names may be included that are trademarks
or service marks of others.
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