Transcript PPT - Microarch.org

Can we design a core that adapts
to the thread-level parallelism in programs?
MorphCore
High performance and energy-efficiency on
both single- and multi-threaded programs
MorphCore
The opposite of previous proposals:
A) The base design: OOO core
B) Then we add in-order SMT
Two modes:
out-of-order core
OutOfOrder
Exploits ILP
High single-thread performance
InOrder
highly-threaded in-order SMT core
Exploits TLP
High multi-thread performance
No OOO execution  Energy savings
By requiring minimal changes to a
traditional OOO core
MorphCore outperforms
• 2- and 4-way SMT
large OOO cores
• Medium OOO cores
• Small in-order cores
• And Core Fusion
MorphCore:
An Energy-Efficient Architecture for
High-Performance ILP and High-Throughput TLP
Khubaib
M. Aater Suleman
Chris Wilkerson
Milad Hashemi
Yale N. Patt
The University of Texas at Austin
Tuesday at 13:30 in Section 5A “Core Design”