Transcript CS136, Advanced Architecture Limits to ILP Simultaneous Multithreading Outline • • • • • • • • Limits to ILP (another perspective) Thread Level Parallelism Multithreading Simultaneous Multithreading Power 4 vs.

CS136, Advanced Architecture
Limits to ILP
Simultaneous Multithreading
Outline
•
•
•
•
•
•
•
•
Limits to ILP (another perspective)
Thread Level Parallelism
Multithreading
Simultaneous Multithreading
Power 4 vs. Power 5
Head to Head: VLIW vs. Superscalar vs. SMT
Commentary
Conclusion
CS136
2
Limits to ILP
• Conflicting studies of amount
– Benchmarks (vectorized Fortran FP vs. integer C programs)
– Hardware sophistication
– Compiler sophistication
• How much ILP is available using existing
mechanisms with increasing HW budgets?
• Do we need to invent new HW/SW
mechanisms to keep on processor
performance curve?
–
–
–
–
CS136
Intel MMX, SSE (Streaming SIMD Extensions): 64 bit ints
Intel SSE2: 128 bit, including 2 64-bit Fl. Pt. per clock
Motorola AltiVec: 128 bit ints and FPs
Supersparc Multimedia ops, etc.
3
Overcoming Limits
• Advances in compiler technology +
significantly new and different hardware
techniques may be able to overcome
limitations assumed in studies
• However, unlikely such advances when
coupled with realistic hardware will
overcome these limits in near future
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Limits to ILP
Initial HW Model here; MIPS compilers.
Assumptions for ideal/perfect machine to start:
1. Register renaming – infinite virtual registers
=> all register WAW & WAR hazards are avoided
2. Branch prediction – perfect; no mispredictions
3. Jump prediction – all jumps perfectly predicted
(returns, case statements)
2 & 3  no control dependencies; perfect speculation
& an unbounded buffer of instructions available
4. Memory-address alias analysis – addresses known
& a load can be moved before a store provided
addresses not equal; 1&4 eliminates all but RAW
Also: perfect caches; 1 cycle latency for all instructions
(FP *,/); unlimited instructions issued/clock cycle
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Limits to ILP HW Model comparison
Model
Power 5
Instructions Issued
per clock
Instruction Window
Size
Renaming
Registers
Branch Prediction
Infinite
4
Infinite
200
Infinite
Cache
Perfect
Memory Alias
Analysis
Perfect
48 integer +
40 Fl. Pt.
2% to 6%
misprediction
(Tournament
Branch Predictor)
64KI, 32KD, 1.92MB
L2, 36 MB L3
??
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Perfect
6
Upper Limit to ILP: Ideal Machine
160
FP: 75 - 150
150.1
140
Instruction Issues per cycle
Instructions Per Clock
(Figure 3.1)
120
Integer: 18 - 60
118.7
100
75.2
80
62.6
60
54.8
40
17.9
20
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Limits to ILP HW Model comparison
New Model
Model
Power 5
Instructions Infinite
Issued per
clock
Instruction
Infinite, 2K, 512,
Window Size 128, 32
Infinite
4
Infinite
200
Renaming
Registers
Infinite
Infinite
48 integer +
40 Fl. Pt.
Branch
Prediction
Perfect
Perfect
Cache
Perfect
Perfect
Memory
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Alias
Perfect
Perfect
2% to 6%
misprediction
(Tournament Branch
Predictor)
64KI, 32KD, 1.92MB
L2, 36 MB L3
??
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More Realistic HW: Window Impact
Figure 3.2
Change from Infinite
window 2048, 512, 128, 32
FP: 9 - 150
160
150
IPC
Instructions Per Clock
140
119
120
Integer: 8 - 63
100
75
80
63
60
40
20
61
55
60
59
49
36
1010 8
41
1513
45
34
35
8
1815
1211 9
1615
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gcc
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Limits to ILP HW Model comparison
New Model
Model
Power 5
Instructions 64
Issued per
clock
Instruction
2048
Window Size
Infinite
4
Infinite
200
Renaming
Registers
Infinite
Infinite
48 integer +
40 Fl. Pt.
Branch
Prediction
Perfect vs. 8K
Tournament vs.
512 2-bit vs.
profile vs. none
Perfect
Cache
Perfect
Perfect
Memory
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Alias
Perfect
Perfect
2% to 6%
misprediction
(Tournament Branch
Predictor)
64KI, 32KD, 1.92MB
L2, 36 MB L3
??
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More Realistic HW: Branch Impact
Figure 3.3
Change from Infinite
window to 2048, and
maximum issue of 64
instructions per clock
cycle
60
50
FP: 15 - 45
60
58
48
46
46
45
45 45
Instruction issues per cycle
IPC
41
40
35
Integer: 6 - 12
30
29
19
20
16
15
13
12
14
10
10
9
6
7
6
6
6
7
4
2
2
2
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Program
Perfect
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Perfect
Tournament
Selective predictor
Standard 2-bit
BHT (512)
Static
Profile
None
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No prediction
Misprediction Rates
35%
30%
Misprediction Rate
30%
23%
25%
18%
20%
18%
16%
14%
15%
14%
12%
12%
10%
6%
5%
5%
4%
3%
1%1%
2%
2%
0%
0%
tomcatv
doduc
fpppp
Profile-based
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2-bit counter
espresso
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Tournament
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Limits to ILP HW Model comparison
New Model
Instructions 64
Issued per
clock
Instruction
2048
Window Size
Model
Power 5
Infinite
4
Infinite
200
Renaming
Registers
Infinite v. 256,
Infinite
128, 64, 32, none
48 integer +
40 Fl. Pt.
Branch
Prediction
8K 2-bit
Perfect
Tournament Branch
Predictor
Cache
Perfect
Perfect
Memory
Alias
Perfect
Perfect
64KI, 32KD, 1.92MB
L2, 36 MB L3
Perfect
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More Realistic HW:
Renaming Register Impact (N int + N fp)
Figure 3.5
FP: 11 - 45
70
60
50
IPC
Change to 2048 instr
window, 64 instr
issue, 8K 2 level
Prediction
59
54
49
45
44
40
35
Instruction issues
per cycle
Integer: 5 - 15
30
29
28
20
20
16
15 15
13
10
11 10 10
12 12 12 11
10
9
5
4
5
11
6
4
15
5
5
5
4
7
5
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Program
Infinite
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Infinite
256
256
128
128
64
32
64
None
32
None
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Limits to ILP HW Model comparison
New Model
Model
Power 5
Instructions 64
Issued per
clock
Instruction
2048
Window Size
Infinite
4
Infinite
200
Renaming
Registers
256 Int + 256 FP
Infinite
48 integer +
40 Fl. Pt.
Branch
Prediction
Cache
8K 2-bit
Perfect
Tournament
Perfect
Perfect
Memory
Alias
Perfect v. Stack
v. Inspect v.
none
Perfect
64KI, 32KD, 1.92MB
L2, 36 MB L3
Perfect
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More Realistic HW:
Memory Address Alias Impact
Figure 3.6
49
50
40
35
Instruction issues per cycle
45
Change 2048 instr
window, 64 instr
issue, 8K 2 level
Prediction, 256
renaming registers
45
IPC
49
30
25
FP: 4 - 45
(Fortran,
no heap)
Integer: 4 - 9
20
45
16
16
15
15
12
10
10
5
9
7
7
4
5
5
4
3
3
4
6
4
3
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Program
Perf ect
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Global/ stack Perf ect
Inspection
None
Global/Stack perf; Compiler None
heap conflicts
Inspection
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4
Limits to ILP HW Model comparison
New Model
Model
Power 5
Instructions
Issued per
clock
Instruction
Window Size
64 (no
restrictions)
Infinite
4
Infinite vs. 256,
128, 64, 32
Infinite
200
Renaming
Registers
64 Int + 64 FP
Infinite
48 integer +
40 Fl. Pt.
Branch
Prediction
Cache
1K 2-bit
Perfect
Tournament
Perfect
Perfect
Memory
Alias
HW
disambiguation
Perfect
64KI, 32KD, 1.92MB
L2, 36 MB L3
Perfect
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Realistic HW: Window Impact
(Figure 3.7)
60
Perfect disambiguation
(HW), 1K Selective
Prediction, 16 entry
return, 64 registers,
issue as many as
window
Integer: 6 - 12
Instruction issues per cycle
50
40
IPC
30
56
52
47
FP: 8 - 45
35
34
22
22
20
15 15
10 10 10
10
9
17 16
14
13
12 12 11 11
10
8
8
6
4
6
3
9
6
4
2
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12
9
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5
4
3
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3
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li
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Program
Inf inite
256
128
Infinite 256 128
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16
64
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Outline
•
•
•
•
•
•
•
•
Limits to ILP (another perspective)
Thread Level Parallelism
Multithreading
Simultaneous Multithreading
Power 4 vs. Power 5
Head to Head: VLIW vs. Superscalar vs. SMT
Commentary
Conclusion
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How to Exceed ILP Limits
of This Study?
• These are not laws of physics
– Just practical limits for today
– Could be overcome via research
• Compiler and ISA advances could change results
• WAR and WAW hazards through memory:
eliminated WAW and WAR hazards through
register renaming, but not in memory usage
– Can get conflicts via allocation of stack frames
– Because called procedure reuses memory addresses of
previous stack frames
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HW v. SW to increase ILP
• Memory disambiguation: HW best
• Speculation:
– HW best when dynamic branch prediction
better than compile-time prediction
– Exceptions easier for HW
– HW doesn’t need bookkeeping code or
compensation code
– Very complicated to get right in SW
• Scheduling: SW can look ahead to
schedule better
• Compiler independence: HW does not
require new compiler to run well
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Performance Beyond Single-Thread ILP
• Much higher natural parallelism in some
applications
– Database or scientific codes
• Explicit thread-level or data-level parallelism
• Thread: has own instructions and data
– May be part of parallel program or independent program
– Each thread has all state (instructions, data, PC, register
state, and so on) needed to execute
• Data-level parallelism: Perform identical
operations on lots of data
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Thread Level Parallelism (TLP)
• ILP exploits implicit parallel operations within
loop or straight-line code segment
• TLP explicitly represented by multiple threads of
execution that are inherently parallel
• Goal: Use multiple instruction streams to
improve
– Throughput of computers that run many programs
– Execution time of multi-threaded programs
• TLP could be more cost-effective to exploit than
ILP
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Do Both ILP and TLP?
• TLP and ILP exploit two different kinds of
parallel structure in a program
• Could a processor oriented to ILP still
exploit TLP?
– Functional units are often idle in data path designed for
ILP because of either stalls or dependencies in the code
• Could TLP be used as source of
independent instructions that might keep
the processor busy during stalls?
• Could TLP be used to employ functional
units that would otherwise lie idle when
insufficient ILP exists?
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New Approach:
Multithreaded Execution
• Multithreading: multiple threads share functional
units of 1 processor via overlapping
– Processor must duplicate independent state of each thread
» Separate copy of register file, PC
» Separate page table if different process
– Memory sharing via virtual memory mechanisms
» Already supports multiple processes
– HW for fast thread switch
» Must be much faster than full process switch (which is
100s to 1000s of clocks)
• When to switch?
– Alternate instruction per thread (fine grain)—round robin
– When thread is stalled (coarse grain)
» E.g., cache miss
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Fine-Grained Multithreading
• Switches between threads on each instruction,
interleaving execution of multiple threads
• Usually done round-robin, skipping stalled
threads
• CPU must be able to switch threads every clock
• Advantage: can hide both short and long stalls
– Instructions from other threads always available to execute
– Easy to insert on short stalls
• Disadvantage: slows individual threads
– Thread ready to execute without stalls will be delayed by
instructions from other threads
• Used on Sun’s Niagara (will see later)
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Course-Grained Multithreading
• Switches threads only on costly stalls
– E.g., L2 cache misses
• Advantages
– Relieves need to have very fast thread switching
– Doesn’t slow thread
» Other threads only issue instructions when main one
would stall (for long time) anyway
• Disadvantage: pipeline startup costs make it hard
to hide throughput losses from shorter stalls
– Pipeline must be emptied or frozen on stall, since CPU
issues instructions from only one thread
– New thread must fill pipe before instructions can
complete
– Thus, better for reducing penalty of high-cost stalls where
pipeline refill << stall time
• Used in IBM AS/400
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Simultaneous Multithreading (SMT)
• Simultaneous multithreading (SMT): insight that
dynamically scheduled processor already has
many HW mechanisms to support multithreading
– Large set of virtual registers that can be used to hold register
sets for independent threads
– Register renaming provides unique register identifiers
» Instructions from multiple threads can be mixed in data
path
» Without confusing sources and destinations across
threads!
– Out-of-order completion allows the threads to execute out of
order, and get better utilization of the HW
• Just add per-thread renaming table and keep
separate PCs
– Independent commitment can be supported via separate
reorder buffer for each thread
Source: Micrprocessor Report, December 6, 1999
“Compaq Chooses SMT for Alpha”
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Simultaneous Multithreading ...
One thread, 8 units
Cycle M M FX FX FP FP BR CC
Two threads, 8 units
Cycle M M FX FX FP FP BR CC
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
M =CS136
Load/Store, FX = Fixed Point, FP = Floating Point, BR = Branch, CC = Condition29Codes
Time (processor cycle)
Multithreaded Categories
Superscalar
Fine-Gr.
Thread 1
Thread 2
CS136
Coarse-Gr.
Multiprocessing
Thread 3
Thread 4
SMT
Thread 5
Idle slot
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Design Challenges in SMT
• What is impact on single thread performance?
– Preferred-thread approach
» Sacrifices neither throughput nor single-thread
performance?
» Nope: processor will sacrifice some throughput when
preferred thread stalls
• Larger register file needed to hold multiple contexts
• Must not affect clock cycle, especially in:
– Instruction issue—more candidate instructions to consider
– Instruction completion—hard to choose which to commit
• Must ensure that cache and TLB conflicts caused
by SMT don’t degrade performance
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Digression: Covert Channels
• Imagine you’re spy with account on Knuth
– Want to communicate a secret to Geoff
– Secret is reasonably small
– FBI is watching your account and your e-mail
• Solution: process spawning
– Once a second, Geoff spawns process
» Records own PID, waits 10 ms, forks & records child PID
– Once a second, you send one bit of information
» If bit is zero, you do nothing
» If bit is one, you spawn processes as fast as possible
– If Geoff sees big PID gap, he records “1”, else “0”
• Many variations on this basic idea
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Covert-Channel Attacks on Crypto
• Most (not all) crypto code behaves differently on
“1” bit in key vs. “0” bit
–
–
–
–
Runs longer or shorter
Uses more or less power
Accesses different memory
Etc.
• Usually called “information leakage”
• Has been successfully used in lab to crack
strong crypto
– Even recovering some bits makes brute-force attack practical
for getting remainder
– Some modern implementations try to fight by doing wasted
work on shorter path of “if”, etc.
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SMT Attack on SSH
• On SMT machine, lower-priority thread’s
execution rate depends on higher-priority one’s
instructions
– More stalls in top thread mean more speed in bottom one
– Stalls vary depending on what crypto code is doing
» Operates at very low level
» Thus much harder to defend against
• Successful attack on ssh keys has been
demonstrated in lab
• Best known defense: don’t do SMT
– Careful coding of crypto could probably also work
– Note that this also applies to things like cache and TLB
– Lots of ways to leak information unintentionally!
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Power 4
Single-threaded predecessor to Power 5. 8
execution units in out-of-order engine; each
can issue instruction each cycle.
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Power 4
Power 5
2 fetch (PC),
2 initial
decodes
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2 commits
(architected
register sets)
36
Power 5 data flow ...
Why only 2 threads? With 4, one of the
shared resources (physical registers, cache,
memory bandwidth) would be prone to
bottleneck
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Power 5 thread performance ...
Relative priority
of each thread
controllable in
hardware.
For balanced
operation, both
threads run
slower than if
they “owned”
the machine.
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Changes in Power 5 to support SMT
• Increased associativity of L1 instruction cache
and instruction address translation buffers
• Added per-thread load and store queues
• Increased size of L2 (1.92 vs. 1.44 MB) and L3
caches
• Added separate instruction prefetch and
buffering per thread
• Increased virtual registers from 152 to 240
• Increased size of several issue queues
• Power5 core is about 24% larger than Power4
because of SMT support
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Initial Performance of SMT
• Pentium 4 Extreme SMT yields 1.01 speedup for
SPECint_rate benchmark; 1.07 for SPECfp_rate
– Pentium 4 is dual-threaded SMT
– SPECRate requires each benchmark to be run against vendorselected number of copies of same benchmark
• Pairing each of 26 SPEC benchmarks with every
other on Pentium 4 (262 runs) gives speedups
from 0.90 to 1.58; average was 1.20
• 8-processor Power 5 server 1.23 faster for
SPECint_rate w/ SMT, 1.16 faster for SPECfp_rate
• Power 5 running 2 copies of each app had
speedup between 0.89 and 1.41
– Most gained some
– Floating-point apps had most cache conflicts and least gains
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Head-to-Head ILP Competition
Processor
Micro architecture
Fetch /
Issue /
Execute
FU
Clock
Rate
(GHz)
Transis
-tors
Die size
Power
Intel
Pentium
4
Extreme
AMD
Athlon 64
FX-57
IBM
Power5
(1 CPU
only)
Intel
Itanium 2
Speculative
dynamically
scheduled; deeply
pipelined; SMT
Speculative
dynamically
scheduled
Speculative
dynamically
scheduled; SMT;
2 CPU cores/chip
Statically
scheduled
VLIW-style
3/3/4
7 int.
1 FP
3.8
125 M
122
mm2
115
W
3/3/4
6 int.
3 FP
2.8
8/4/8
6 int.
2 FP
1.9
6/5/11
9 int.
2 FP
1.6
114 M 104
115
W
mm2
200 M 80W
300 (est.)
mm2
(est.)
592 M 130
423
W
mm2
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Performance on SPECint2000
Itanium 2
Pentium 4
AMD Athlon 64
Pow er 5
3500
3000
2500
2000
SPEC Ratio
15 0 0
10 0 0
500
0
gzip
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Performance on SPECfp2000
14000
Itanium 2
Pentium 4
AMD Athlon 64
Power 5
12000
10000
8000
SPEC Ratio
6000
4000
2000
0
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Normalized Performance: Efficiency
35
Itanium 2
Pentium 4
AMD Athlon 64
POWER 5
30
25
Rank
20
Int/Trans
FP/Trans
15
A
t
h
l
o
n
4 2 1 3
4 2 1 3
Int/Watt
FP/Watt
2 4 3 1
10
FP/area
0
SPECInt / M SPECFP / M
Transistors Transistors
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SPECInt /
mm^2
SPECFP /
mm^2
SPECInt /
Watt
P
o
w
e
r
5
4 2 1 3
4 2 1 3
4 3 1 2
Int/area
5
I P
t
e
a n
n
t
i
I
u u
m m
2 4
SPECFP /
Watt
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No Silver Bullet for ILP
• No obvious overall leader in performance
• AMD Athlon leads on SPECInt performance,
followed by the Pentium 4, Itanium 2, and Power5
• Itanium 2 and Power5 clearly dominate Athlon
and Pentium 4 on SPECFP
• Itanium 2 is most inefficient processor both for
floating-point and integer code for all but one
efficiency measure (SPECFP/Watt)
• Athlon and Pentium 4 both use transistors and
area efficiently
• IBM Power5 is most effective user of energy on
SPECFP, essentially tied on SPECINT
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Limits to ILP
• Doubling issue rates above today’s 3-6
instructions per clock probably requires
processor to:
–
–
–
–
Issue 3-4 data-memory accesses per cycle,
Resolve 2-3 branches per cycle,
Rename and access over 20 registers per cycle, and
Fetch 12-24 instructions per cycle.
• Complexity of implementing these capabilities is
likely to mean sacrifices in maximum clock rate
– E.g, widest-issue processor is Itanium 2
– It also has slowest clock rate
– Despite consuming the most power!
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Limits to ILP (cont’d)
• Most ways to increase performance also boost
power consumption
• Key question is energy efficiency: does a method
increase power consumption faster than it boosts
performance?
• Multiple-issue techniques are energy inefficient:
– Incurs logic overhead that grows faster than issue rate
– Growing gap between peak issue rates and sustained
performance
• Number of transistors switching = f(peak issue
rate); performance = f(sustained rate);
growing gap between peak and sustained
performance
 Increasing energy per unit of performance
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Commentary
• Itanium is not significant breakthrough in scaling
ILP or in avoiding problems of complexity and
power consumption
• Instead of pursuing more ILP, architects turning
to TLP using single-chip multiprocessors
• In 2000, IBM announced Power4, 1st commercial
single-chip, general-purpose multiprocessor: has
two Power3 processors and integrated L2 cache
– Sun Microsystems, AMD, and Intel have also switched focus
from aggressive uniprocessors to single-chip multiprocessors
• Right balance of ILP and TLP is unclear today
– Maybe desktops (mostly single-threaded?) need different
design than servers (can do lots of TLP)
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And in conclusion …
• Limits to ILP (power efficiency, compilers,
dependencies …) seem to limit to 3 to 6 issue for
practical options
• Explicitly parallel (Data level parallelism or
Thread level parallelism) is next step to
performance
• Coarse grain vs. Fine grained multihreading
– Only on big stall vs. every clock cycle
• Simultaneous Multithreading if fine grained
multithreading based on OOO superscalar
microarchitecture
– Instead of replicating registers, reuse rename registers
• Itanium/EPIC/VLIW is not a breakthrough in ILP
• Balance of ILP and TLP decided in marketplace
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