Transcript Progress Presentation (3/1/2011)

Comprehensive Ultrasound
Research Platform
Emma Muir
Sam Muir
Jacob Sandlund
David Smith
Advisor: Dr. Sánchez
Co-advisor: Dr. Irwin
Outline
Introduction
 System

◦ Block Diagram / Functional Description
◦ Requirements

Progress
2
Outline
Introduction
 System

◦ Block Diagram / Functional Description
◦ Requirements

Progress
3
Ultrasound Introduction

Piezoelectric Transducer
◦ Pulse Excitation

Changes in density reflect waves
4
Objective

Create an Ultrasound Research Platform
◦ Image Creation
◦ Multi-pin
 Beamforming
◦ Sigma Delta Architecture
 1-bit ADC
◦ Arbitrary Waveforms
 Coded excitation signals
 Configurable delays
5
Motivation
Improve Ultrasound Techniques
 Medical Applications

◦ Detecting tumors and abnormalities

Future Research
6
Significance
Test codes (arbitrary) for
better imaging
 Multi-pin to allow
Beamforming
 Architecture reduces cost
and size

◦ RASMUS
 Two 19 inch racks
◦ Sigma Delta vs. 12+ bit DAC
7
Outline
Introduction
 System

◦ Block Diagram / Functional Description
◦ Requirements

Progress
8
Block Diagram
Arbitrary
Waveform
High Voltage
Amplifier
Analog Front
End
Sigma Delta
Modulation
Low-Pass
Filter
Embedded
Device
FPGA
128-element
Ultrasonic
Array
PC
Tx/Rx Switch
9
PC Data Processing
Receive Data
Pulse
Compression
Delay Sum
Beamforming
Time-Gain
Compensation
Envelope
Detection
Log
Compression
GUI
10
Outline
Introduction
 System

◦ Block Diagram / Functional Description
◦ Requirements

Progress
11
System Requirements
 Up to 8 transducer channels
 Excitations
<= 3 μs
◦ Time-bandwidth product of 40
 High frequency design
◦ Signal to noise ratio (SNR) > 50 dB
12
Sigma Delta Modulation
 < 10% MSE
 500 M samples/second
 Trade off
◦ Accuracy vs. Stability
◦ OSR = 16 (must be a power of 2)
◦ Order = 2nd
13
FPGA Requirements

Store data on DDR2
◦ 62.5 MHz
◦ 8 waveforms
◦ 1536 bits per waveform

Output Data
◦ 8 Individualized Pins
◦ Delays of up to 5 ms
◦ 500 MHz
14
FPGA to PC Communication

UART
◦ 115200 baud
Send waveform data
 Assign waveform to pins
 Assign delay to pins
 Start transmission

15
Graphical User Interface (GUI)

Data Processing
◦ Less than 2 minutes

Display an image
◦ Depths between 0.25 cm and 30 cm.
◦ Adjust contrast
16
Outline
Introduction
 System

◦ Block Diagram / Functional Description
◦ Requirements

Progress
17
Progress
Feb 2011
ID
Mar 2011
Apr 2011
Task Name
% Complete
1/23
1/30
2/6
2/13
2/20
2/27
3/6
3/13
3/20
3/27
4/3
4/10
4/17
4/24 5/1
1
Design and Test Analog Components
40%
2
Test Amplifier with Sigma Delta Signal
0%
3
Test Complete Analog System/Probe
0%
4
Finalize FPGA Signal Transmission
90%
5
Create / Test UART connection logic
100%
6
Test UART / FPGA Outputs
70%
7
Design Analog Front End Settings
15%
8
Test Analog Front End Capturing
0%
9
Design / Test Delay Sum Beamforming
100%
10
Design and Test all MATLAB code
90%
11
Design GUI for Depth/Contrast
100%
12
Rewrite MATLAB code in C
0%
13
Combine and Test all C Code
0%
14
Test Complete System
0%
15
Write Presentation and Final Report
0%
16
Final Presentation
0%
17
2011 Student Scholarship Exposition
0%
18
Progress
Feb 2011
ID
Mar 2011
Apr 2011
Task Name
% Complete
1/23
1/30
2/6
2/13
2/20
2/27
3/6
3/13
3/20
3/27
4/3
4/10
4/17
4/24 5/1
1
Design and Test Analog Components
40%
2
Test Amplifier with Sigma Delta Signal
0%
3
Test Complete Analog System/Probe
0%
4
Finalize FPGA Signal Transmission
90%
5
Create / Test UART connection logic
100%
6
Test UART / FPGA Outputs
70%
7
Design Analog Front End Settings
15%
8
Test Analog Front End Capturing
0%
9
Design / Test Delay Sum Beamforming
100%
10
Design and Test all MATLAB code
90%
11
Design GUI for Depth/Contrast
100%
12
Rewrite MATLAB code in C
0%
13
Combine and Test all C Code
0%
14
Test Complete System
0%
15
Write Presentation and Final Report
0%
16
Final Presentation
0%
17
2011 Student Scholarship Exposition
0%
19
Amplifier Progress

Different designs examined
◦ H-Bridge
◦ 2 MOSFETs
 Push-pull RF MOSFET
◦ 1 MOSFET
 N-channel RF MOSFET
 Final Design
20
Amplifier Progress

Discuss problems/solutions
Amplifier Progress
Amplifier Progress
Amplifier Progress
Amplifier Progress
Amplifier Progress
T/R Switch Progress
0
0
V1
5
V2
5
OUT1
VD
VP
22
24
C1
U1
TX810
5
6
7
8
9
10
11
12
V9
13
14
15
16
17
18
19
20
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
4
23
21
3
2
1
0
VB
OUT2
15p
C3
VB
OUT3
15p
C4
VB
OUT4
15p
R2
R3
R4
R5
400
400
400
400
C5
OUT5
GND
VN
VB
B3
B2
B1
VOFF = 0
VAMPL = X
FREQ = 2Meg
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
15p
C2
15p
C6
VB
OUT6
15p
C7
VB
OUT7
15p
VB
C8
VB
OUT8
15p
R6
R7
R8
R9
400
400
400
400
VB
VB
V4
-5
0
0
V6
0
0
V8
5
0
V5
5
0
V7
5
0
27
T/R Switch Progress
1.92V
2.0V
1.5V
1.0V
0.5V
-0.0V
-0.5V
-1.0V
0s
V(OUT1)
0.2us
0.4us
MAX(V(OUT1))- MIN(V(OUT1))
0.6us
0.8us
1.0us
1.2us
1.4us
1.6us
1.8us
2.0us
Time
28
PCB Progress

Footprints
◦ TX810
 Transmit/Receive
Switch
◦ RF MOSFET
 Set INTO board
Progress
Feb 2011
ID
Mar 2011
Apr 2011
Task Name
% Complete
1/23
1/30
2/6
2/13
2/20
2/27
3/6
3/13
3/20
3/27
4/3
4/10
4/17
4/24 5/1
1
Design and Test Analog Components
40%
2
Test Amplifier with Sigma Delta Signal
0%
3
Test Complete Analog System/Probe
0%
4
Finalize FPGA Signal Transmission
90%
5
Create / Test UART connection logic
100%
6
Test UART / FPGA Outputs
70%
7
Design Analog Front End Settings
15%
8
Test Analog Front End Capturing
0%
9
Design / Test Delay Sum Beamforming
100%
10
Design and Test all MATLAB code
90%
11
Design GUI for Depth/Contrast
100%
12
Rewrite MATLAB code in C
0%
13
Combine and Test all C Code
0%
14
Test Complete System
0%
15
Write Presentation and Final Report
0%
16
Final Presentation
0%
17
2011 Student Scholarship Exposition
0%
30
Progress
Feb 2011
ID
Mar 2011
Apr 2011
Task Name
% Complete
1/23
1/30
2/6
2/13
2/20
2/27
3/6
3/13
3/20
3/27
4/3
4/10
4/17
4/24 5/1
1
Design and Test Analog Components
40%
2
Test Amplifier with Sigma Delta Signal
0%
3
Test Complete Analog System/Probe
0%
4
Finalize FPGA Signal Transmission
90%
5
Create / Test UART connection logic
100%
6
Test UART / FPGA Outputs
70%
7
Design Analog Front End Settings
15%
8
Test Analog Front End Capturing
0%
9
Design / Test Delay Sum Beamforming
100%
10
Design and Test all MATLAB code
90%
11
Design GUI for Depth/Contrast
100%
12
Rewrite MATLAB code in C
0%
13
Combine and Test all C Code
0%
14
Test Complete System
0%
15
Write Presentation and Final Report
0%
16
Final Presentation
0%
17
2011 Student Scholarship Exposition
0%
31
Progress
Feb 2011
ID
Mar 2011
Apr 2011
Task Name
% Complete
1/23
1/30
2/6
2/13
2/20
2/27
3/6
3/13
3/20
3/27
4/3
4/10
4/17
4/24 5/1
1
Design and Test Analog Components
40%
2
Test Amplifier with Sigma Delta Signal
0%
3
Test Complete Analog System/Probe
0%
4
Finalize FPGA Signal Transmission
90%
5
Create / Test UART connection logic
100%
6
Test UART / FPGA Outputs
70%
7
Design Analog Front End Settings
15%
8
Test Analog Front End Capturing
0%
9
Design / Test Delay Sum Beamforming
100%
10
Design and Test all MATLAB code
90%
11
Design GUI for Depth/Contrast
100%
12
Rewrite MATLAB code in C
0%
13
Combine and Test all C Code
0%
14
Test Complete System
0%
15
Write Presentation and Final Report
0%
16
Final Presentation
0%
17
2011 Student Scholarship Exposition
0%
32
FPGA Progress
Arbitrary transmission
 Output verified

◦ 500 MHz

Multi-pin
◦ Currently 4
◦ Adjustable

Arbitrary length
◦ Must be 256 bit pieces

Adjustable delays of < 33 ms
33
FPGA Flowchart Progress
Receive
Waveform
Data
(UART)
Store to
Memory
Request
Waveform Data
(X8)
Delay
Delay(X8)
(X8)
Is Data
Received?
No
Is Signal to
Transmit
Yes
Transmit to
Pin
(X8)
34
FPGA Remaining

Fix storing waveform data from UART
◦ Inconsistent results

Increase delays precision
◦ After data retrieved
Make output more exact
 Change to 8 pins

35
Progress
Feb 2011
ID
Mar 2011
Apr 2011
Task Name
% Complete
1/23
1/30
2/6
2/13
2/20
2/27
3/6
3/13
3/20
3/27
4/3
4/10
4/17
4/24 5/1
1
Design and Test Analog Components
40%
2
Test Amplifier with Sigma Delta Signal
0%
3
Test Complete Analog System/Probe
0%
4
Finalize FPGA Signal Transmission
90%
5
Create / Test UART connection logic
100%
6
Test UART / FPGA Outputs
70%
7
Design Analog Front End Settings
15%
8
Test Analog Front End Capturing
0%
9
Design / Test Delay Sum Beamforming
100%
10
Design and Test all MATLAB code
90%
11
Design GUI for Depth/Contrast
100%
12
Rewrite MATLAB code in C
0%
13
Combine and Test all C Code
0%
14
Test Complete System
0%
15
Write Presentation and Final Report
0%
16
Final Presentation
0%
17
2011 Student Scholarship Exposition
0%
36
UART Progress

UART
◦ 115200 baud works

PC to FPGA Communication
◦
◦
◦
◦
Start transmission signal
Set waveforms to pins
Set delays for pins
Waveform data
 Inconsistent
37
38
Waveform GUI Features
Multiple selection
 Automatic pin settings removal
 Save/Load settings
 Check files exist when loading settings
 Let “None” represent an array of 0’s

39
Progress
Feb 2011
ID
Mar 2011
Apr 2011
Task Name
% Complete
1/23
1/30
2/6
2/13
2/20
2/27
3/6
3/13
3/20
3/27
4/3
4/10
4/17
4/24 5/1
1
Design and Test Analog Components
40%
2
Test Amplifier with Sigma Delta Signal
0%
3
Test Complete Analog System/Probe
0%
4
Finalize FPGA Signal Transmission
90%
5
Create / Test UART connection logic
100%
6
Test UART / FPGA Outputs
70%
7
Design Analog Front End Settings
15%
8
Test Analog Front End Capturing
0%
9
Design / Test Delay Sum Beamforming
100%
10
Design and Test all MATLAB code
90%
11
Design GUI for Depth/Contrast
100%
12
Rewrite MATLAB code in C
0%
13
Combine and Test all C Code
0%
14
Test Complete System
0%
15
Write Presentation and Final Report
0%
16
Final Presentation
0%
17
2011 Student Scholarship Exposition
0%
40
FPGA Results
V
o
l
t
a
g
e
10
Delayed
5
0
-5
-2
-1
0
2
3
Time (s)
Cross-talk
V
o
l
t
a
g
e
1
4
-6
x 10
Cross-talk
10
5
0
-5
-2
-1
0
1
Time (s)
2
3
4
-6
x 10
41
FPGA Results
Normalized Correlation
1.2
1
Max Corr. = 0.97
0.8
0.6
0.4
0.2
0
-0.2
-5
0
Sample number
5
4
x 10
42
FPGA Results
43
FPGA Results
44
FPGA Results
45
Progress
Feb 2011
ID
Mar 2011
Apr 2011
Task Name
% Complete
1/23
1/30
2/6
2/13
2/20
2/27
3/6
3/13
3/20
3/27
4/3
4/10
4/17
4/24 5/1
1
Design and Test Analog Components
40%
2
Test Amplifier with Sigma Delta Signal
0%
3
Test Complete Analog System/Probe
0%
4
Finalize FPGA Signal Transmission
90%
5
Create / Test UART connection logic
100%
6
Test UART / FPGA Outputs
70%
7
Design Analog Front End Settings
15%
8
Test Analog Front End Capturing
0%
9
Design / Test Delay Sum Beamforming
100%
10
Design and Test all MATLAB code
90%
11
Design GUI for Depth/Contrast
100%
12
Rewrite MATLAB code in C
0%
13
Combine and Test all C Code
0%
14
Test Complete System
0%
15
Write Presentation and Final Report
0%
16
Final Presentation
0%
17
2011 Student Scholarship Exposition
0%
46
Analog Front End Results
Source: Analog Devices UG-016 http://www.analog.com/static/imported-files/user_guides/UG-016.pdf
47
Alternatives

Analog Front End
◦ 12 bit resolution
◦ 80 MSPS

Lecroy High Speed Oscilloscope
◦
◦
◦
◦
725Zi
8 bit Resolution
20 GSPS
4 Channels
48
Progress
Feb 2011
ID
Mar 2011
Apr 2011
Task Name
% Complete
1/23
1/30
2/6
2/13
2/20
2/27
3/6
3/13
3/20
3/27
4/3
4/10
4/17
4/24 5/1
1
Design and Test Analog Components
40%
2
Test Amplifier with Sigma Delta Signal
0%
3
Test Complete Analog System/Probe
0%
4
Finalize FPGA Signal Transmission
90%
5
Create / Test UART connection logic
100%
6
Test UART / FPGA Outputs
70%
7
Design Analog Front End Settings
15%
8
Test Analog Front End Capturing
0%
9
Design / Test Delay Sum Beamforming
100%
10
Design and Test all MATLAB code
90%
11
Design GUI for Depth/Contrast
100%
12
Rewrite MATLAB code in C
0%
13
Combine and Test all C Code
0%
14
Test Complete System
0%
15
Write Presentation and Final Report
0%
16
Final Presentation
0%
17
2011 Student Scholarship Exposition
0%
49
Progress
Feb 2011
ID
Mar 2011
Apr 2011
Task Name
% Complete
1/23
1/30
2/6
2/13
2/20
2/27
3/6
3/13
3/20
3/27
4/3
4/10
4/17
4/24 5/1
1
Design and Test Analog Components
40%
2
Test Amplifier with Sigma Delta Signal
0%
3
Test Complete Analog System/Probe
0%
4
Finalize FPGA Signal Transmission
90%
5
Create / Test UART connection logic
100%
6
Test UART / FPGA Outputs
70%
7
Design Analog Front End Settings
15%
8
Test Analog Front End Capturing
0%
9
Design / Test Delay Sum Beamforming
100%
10
Design and Test all MATLAB code
90%
11
Design GUI for Depth/Contrast
100%
12
Rewrite MATLAB code in C
0%
13
Combine and Test all C Code
0%
14
Test Complete System
0%
15
Write Presentation and Final Report
0%
16
Final Presentation
0%
17
2011 Student Scholarship Exposition
0%
50
Beamforming
Sensors
Focal Point
Point
Delay based on distance from point to sensor and distance from sensor to focal point
Note: No delay at the Focal Point
51
Without Beamforming
With Beamforming
52
Attenuation

Average frequency attenuation in tissue
◦ 0.5 dB/cm/MHz
◦ 5e-5 dB/m/Hz





Doubled for ultrasound imaging
Frequency = 8MHz
Maximum depth = 30cm
Maximum attenuation = 240dB
Image dB range = 0dB to -50dB
53
Time Gain Compensation
Based on depth of point in image
 Att = 1dB/cm/MHz
 TGC = Att*Depth*8MHz
 Add to compensate
 Note that this increases white noise for
larger depths

54
Progress
Feb 2011
ID
Mar 2011
Apr 2011
Task Name
% Complete
1/23
1/30
2/6
2/13
2/20
2/27
3/6
3/13
3/20
3/27
4/3
4/10
4/17
4/24 5/1
1
Design and Test Analog Components
40%
2
Test Amplifier with Sigma Delta Signal
0%
3
Test Complete Analog System/Probe
0%
4
Finalize FPGA Signal Transmission
90%
5
Create / Test UART connection logic
100%
6
Test UART / FPGA Outputs
70%
7
Design Analog Front End Settings
15%
8
Test Analog Front End Capturing
0%
9
Design / Test Delay Sum Beamforming
100%
10
Design and Test all MATLAB code
90%
11
Design GUI for Depth/Contrast
100%
12
Rewrite MATLAB code in C
0%
13
Combine and Test all C Code
0%
14
Test Complete System
0%
15
Write Presentation and Final Report
0%
16
Final Presentation
0%
17
2011 Student Scholarship Exposition
0%
55
Sigma Delta Representation
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0
1
2
3
4
5
6
7
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0
1
2
3
4
5
6
56
Without Pre-Enhanced Magnitude
1
0.5
0
-0.5
-1
0
0.2
0.4
0.6
0.8
1
1.2
-5
x 10
1
0.5
0
-0.5
-1
0
0.2
0.4
0.6
0.8
1
1.2
-5
x 10
Correlation = 0.9763
57
Pre-Enhanced Magnitude
2
1
0
-1
-2
0
0.5
1
1.5
2
2.5
3
-6
x 10
1
0.5
0
-0.5
-1
0
0.5
1
1.5
2
2.5
3
-6
x 10
58
With Pre-Enhanced Magnitude
1
0.5
0
-0.5
-1
0
0.2
0.4
0.6
0.8
1
1.2
-5
x 10
1
0.5
0
-0.5
-1
0
0.2
0.4
0.6
0.8
1
1.2
-5
x 10
Correlation = 0.9916
59
Sigma Delta Features

Easy to modify
◦
◦
◦
◦
Frequency
Period
Waveform equation
Number of samples
Pre-Enhanced Magnitude
 Checks/displays correlation
 Writes output to a file as 0’s and 1’s

60
Sigma Delta Additions

GUI interface for entering
◦ Frequency
◦ Period
◦ Waveform equation
Select location to save file
 Interface with Waveform GUI

61
REC Results
MATLAB simulation
 150% of original bandwidth
 Linear chirp frequencies

◦ 1.14 times the bandwidth
◦ Reduce side-lobes during pulse compression

Apply to finished system
62
h1(n) * c1(n) = h2(n) * c2(n)
63
64
Pulse Compression Results
MATLAB simulation
 Wiener filter
 SNR of 60 dB
 Input is REC pre-enhanced chirp
 Varied Smoothing Factor (SF)

◦ Operating Point
65
66
Field II Simulations
REC Excitation and Pulse Compression
SF = 0.1
Impulse Excitation
67
Progress
Feb 2011
ID
Mar 2011
Apr 2011
Task Name
% Complete
1/23
1/30
2/6
2/13
2/20
2/27
3/6
3/13
3/20
3/27
4/3
4/10
4/17
4/24 5/1
1
Design and Test Analog Components
40%
2
Test Amplifier with Sigma Delta Signal
0%
3
Test Complete Analog System/Probe
0%
4
Finalize FPGA Signal Transmission
90%
5
Create / Test UART connection logic
100%
6
Test UART / FPGA Outputs
70%
7
Design Analog Front End Settings
15%
8
Test Analog Front End Capturing
0%
9
Design / Test Delay Sum Beamforming
100%
10
Design and Test all MATLAB code
90%
11
Design GUI for Depth/Contrast
100%
12
Rewrite MATLAB code in C
0%
13
Combine and Test all C Code
0%
14
Test Complete System
0%
15
Write Presentation and Final Report
0%
16
Final Presentation
0%
17
2011 Student Scholarship Exposition
0%
68
MATLAB GUI Features
Depth from 2mm to 231mm
 Max dB range from 10dB to 60dB
 Update chart settings automatically
 Update data in 54s

69
MATLAB GUI
70
MATLAB GUI
71
MATLAB GUI Additions
Depth from 2mm to 300mm
 Restrict max dB to 40dB to 60dB
 Allow user to type value or scroll
 Minimize update time
 Convert to C

72
Progress
Feb 2011
ID
Mar 2011
Apr 2011
Task Name
% Complete
1/23
1/30
2/6
2/13
2/20
2/27
3/6
3/13
3/20
3/27
4/3
4/10
4/17
4/24 5/1
1
Design and Test Analog Components
40%
2
Test Amplifier with Sigma Delta Signal
0%
3
Test Complete Analog System/Probe
0%
4
Finalize FPGA Signal Transmission
90%
5
Create / Test UART connection logic
100%
6
Test UART / FPGA Outputs
70%
7
Design Analog Front End Settings
15%
8
Test Analog Front End Capturing
0%
9
Design / Test Delay Sum Beamforming
100%
10
Design and Test all MATLAB code
90%
11
Design GUI for Depth/Contrast
100%
12
Rewrite MATLAB code in C
0%
13
Combine and Test all C Code
0%
14
Test Complete System
0%
15
Write Presentation and Final Report
0%
16
Final Presentation
0%
17
2011 Student Scholarship Exposition
0%
73
Progress
Feb 2011
ID
Mar 2011
Apr 2011
Task Name
% Complete
1/23
1/30
2/6
2/13
2/20
2/27
3/6
3/13
3/20
3/27
4/3
4/10
4/17
4/24 5/1
1
Design and Test Analog Components
40%
2
Test Amplifier with Sigma Delta Signal
0%
3
Test Complete Analog System/Probe
0%
4
Finalize FPGA Signal Transmission
90%
5
Create / Test UART connection logic
100%
6
Test UART / FPGA Outputs
70%
7
Design Analog Front End Settings
15%
8
Test Analog Front End Capturing
0%
9
Design / Test Delay Sum Beamforming
100%
10
Design and Test all MATLAB code
90%
11
Design GUI for Depth/Contrast
100%
12
Rewrite MATLAB code in C
0%
13
Combine and Test all C Code
0%
14
Test Complete System
0%
15
Write Presentation and Final Report
0%
16
Final Presentation
0%
17
2011 Student Scholarship Exposition
0%
74
Progress
Feb 2011
ID
Mar 2011
Apr 2011
Task Name
% Complete
1/23
1/30
2/6
2/13
2/20
2/27
3/6
3/13
3/20
3/27
4/3
4/10
4/17
4/24 5/1
1
Design and Test Analog Components
40%
2
Test Amplifier with Sigma Delta Signal
0%
3
Test Complete Analog System/Probe
0%
4
Finalize FPGA Signal Transmission
90%
5
Create / Test UART connection logic
100%
6
Test UART / FPGA Outputs
70%
7
Design Analog Front End Settings
15%
8
Test Analog Front End Capturing
0%
9
Design / Test Delay Sum Beamforming
100%
10
Design and Test all MATLAB code
90%
11
Design GUI for Depth/Contrast
100%
12
Rewrite MATLAB code in C
0%
13
Combine and Test all C Code
0%
14
Test Complete System
0%
15
Write Presentation and Final Report
0%
16
Final Presentation
0%
17
2011 Student Scholarship Exposition
0%
75
Additional Information
Visit http://cegt201.bradley.edu/projects/
proj2011/ultra/index.html

76
Acknowledgments







The authors would like to thank Analog Devices
and Texas instruments for their donation of parts.
This work is partially supported by a grant from
Bradley University (13 26 154 REC)
Dr. Irwin
Dr. Lu
Mr. Mattus
Mr. Schmitt
Andy Fouts
77
References
[1] J. A. Zagzebski, Essentials of Ultrasound Physics, St. Louis, MO: Mosby, 1996.
[2] R. Schreier and G. C. Temes. Understanding Delta-Sigma Data Converters, John
Wiley & Sons, Inc., 2005.
[3] R. Schreier, The Delta-Sigma Toolbox Version 7.3. Analog Devices, Inc, 2009.
[4] T. Misaridis and J. A. Jensen. “Use of Modulated Excitation Signals in
Medical Ultrasound,” IEEE Trans. Ultrason., Ferroelectr. Freq. Contr., vol. 52, no. 2,
pp. 177-191, Feb. 2005.
[5] M. Oelze. “Bandwidth and Resolution Enhancement
Through Pulse Compression,” IEEE Trans. Ultrason., Ferroelectr. Freq. Contr., vol. 54,
no. 4, pp. 768-781, Apr. 2007.
[6] Mitzner, Kraig. Complete PCB Design Using OrCad Capture and PCB Editor,
Newnes, 2009.
78
References Cont.
[7] Montrose, Mark I. Printed Circuit Board Design Techniques For EMC Compliance:
A Handbook for Designers, Wiley-IEEE Press, 2000.
[8] J.A. Jensen. Field: A Program for Simulating Ultrasound Systems, Paper presented
at the 10th Nordic-Baltic Conference on Biomedical Imaging Published in Medical &
Biological Engineering & Computing, pp. 351-353, Volume 34, Supplement 1, Part 1,
1996.
[9] Kai E. Thomenius. Evolution of Ultrasound Beamformers, IEEE Trans. Ultrason.,
Ferroelectr. Freq. Contr., pp. 1615-1622, 1996.
[10] J.A. Jensen and N. B. Svendsen. Calculation of pressure fields from arbitrarily
shaped, apodized, and excited ultrasound transducers, IEEE Trans. Ultrason.,
Ferroelec., Freq. Contr., 39, pp. 262-267, 1992.
[11] Kjærgaard, Nina. "RASMUS." Center for Fast Ultrasound Imaging. Technical
University of Denmark, 28 Sept. 2010. Web. 25 Feb. 2011.
<http://www.dtu.dk/centre/cfu/English/research/facilities/RASMUS.aspx>.
79
Questions?
80
Without TGC
With TGC
81
Using Delta as the Excitation Signal
Using REC (chirp)
82