Transcript Lab06

數位系統實驗
Experiment on Digital System
Lab06:
Verilog HDL and FPGA (2)
負責助教：葉俊顯 stanley
Outline
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Introduction to VeriLite
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Programming VeriLite
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Verification using VeriInstrument
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Lab
2015/4/13
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Outline

Introduction to VeriLite

Programming VeriLite

Verification using VeriInstrument

Lab
2015/4/13
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Introduction to VeriLite
USB
開關
電源線
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Reset
JTAG
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Introduction to VeriLite
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Introduction to VeriLite
虛擬元件
利用 USB 溝通
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Outline

Introduction to VeriLite

Programming VeriLite

Verification using VeriInstrument

Lab
2015/4/13
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Programming VeriLite
一般組合電路不會有 clk 訊號出現，clk只會
在循序電路出現
備註：此 FPGA 板子需要額外的 clk 訊號
腳位設定才可以動作，所以務必記得加入
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Programming VeriLite
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Start compilation
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Programming VeriLite
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Open Assignment editor
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Programming VeriLite
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Show input and output pins
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Programming VeriLite
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Pin assignment
Double click
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Programming VeriLite
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Assign pin location to all inputs and outputs and add Clk
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Please refer to pin.xls for pin location assignment
Clock must be assigned to location Pin_28
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Programming VeriLite
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Start compilation
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Programming VeriLite
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Programming device
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Programming VeriLite
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Hardware setup: add USB-Blaster
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Programming VeriLite
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Programming device
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Outline

Introduction to VeriLite

Programming VeriLite

Verification using VeriInstrument

Lab
2015/4/13
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Verification using VeriInstrument
一定要先確認!!!
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Verification using VeriInstrument
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Specify the name of project file and the pin information
file (*.qsf) generated by QuartusII
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Verification using VeriInstrument
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Check pin assignment
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Verification using VeriInstrument
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Add I/O device
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Verification using VeriInstrument
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Add I/O device
Drag here
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Verification using VeriInstrument
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Assign user pins
Drag here
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Verification using VeriInstrument
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Run FPGA
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Outline

Introduction to VeriLite

Programming VeriLite

Verification using VeriInstrument

Lab
2015/4/13
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Lab
2-Bit by 2-Bit Binary Multiplier
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A0
B1
x
+
C3
A1B1
C2
B1
B0
A1
A0B1
A1B0
C1
A0
A0B0
B0
A1
B1
B0
HA
HA
C2
C1
C0
Four input, B1,B0, A1,A0
Four output, C3, C2, C1, C0
C3
C0
Lab
Hint
x
S
C
y
reg s,c;
always @(x or y)
begin
xor xor01(s, x, y);
and and01(c, x, y);
s=x^y;
c=x&y;
assign s=x^y;
assign c=x&y;
end
Notice
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請勿在桌面建立 Project 及請勿命名中文資料夾
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Device family 請確認與 FPGA Chip 符合 (EP1C6Q240C8)
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Top module name & Project name 需要一致
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確認 module … endmodule 為keyword 變成藍色字體
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