Transcript Document

數位系統實驗
Experiment on Digital System
Lab05:
IC design flow and FPGA
Introduction to Verilog HDL
負責助教：葉俊顯 stanley
Outline

IC Design Flow and FPGA

Introduction to HDL

Write Verilog code using Quartus II

Lab
2015/7/20
2
Outline

IC Design Flow and FPGA

Introduction to HDL

Write Verilog code using Quartus II

Lab
2015/7/20
3
Digital system

Digital system
 數位系統 (digital system) 通常被設計用來實現或完成
某一些特殊的功能需求



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MP3 player
Mobile phone
…
一個數位系統可能包含數個不同功能特質的數位電路，
而數位電路一般是使用所謂的半導體技術實作於積體電路
(Integrated circuit, IC) 上
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IC design flow
Product specification
Sim/Ver
Circuit design
Sim/Ver
Layout
(placement & routing)
GDS-II
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ASIC and FPGA

當設計者完成RTL(Register Transfer Level)電路後，若使用製作
功能應用導向晶片(Application Specific Integrated Circuit，ASIC)
的EDA tools來進行合成、模擬、驗證，最後，會產生一個GDSII檔案。最後，可將此檔案委請晶圓廠製成一顆ASIC晶片

FPGA/CPLD是一種可依需要做程式規劃的晶片，其中包含許多
可被使用的cells，透過FPGA廠商提供的FPGA-EDA tool進行合
成、模擬與驗證，最後將所設計的電路燒錄到FPGA上面


FPGA (Field Programmable Gate Array) – 本課程所使用
CPLD (Complex Programmable Logic Device)
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FPGA design flow
Design ideas
Detailed design
Functional simulation
Implementation
(P & R)
Time simulation
Device programming
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Outline

IC Design Flow and FPGA

Introduction to HDL

Write Verilog code using Quartus II

Lab
2015/7/20
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Introduction to HDL

HDL
 Hardware description language
 Similar to general-purpose languages like C
 Modeling and simulation of the functionality of
combinational and sequential circuits
 Parallel vs. sequential behaviors
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Two competitive forces
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Verilog: C-like language – 本課程所使用
VHDL: ADA-like language
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Introduction to Verilog HDL
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C-like syntax/semantics
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Basic building block

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Module
Four kinds of model for circuits
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
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Switch Level Model or Transistor Model (npn & pnp …)
Gate Level Model (or & and …)
Data Flow Model (assign)
Behavioral Model (RTL description) (always@() begin … end)
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Design hierarchy
output1
input1
top_module
sub_module1
output2
input2
output3
input3
sub_module2
sub_module3
output4
input4
output5
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Identifier
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Names of modules, ports, wires and instances are all
identifiers
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First character must be a letter, and other characters can
be letters, numbers or underscore ( _ )
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Upper case and lower case letters are different
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Keyword
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All keywords are defined in lower case
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Keyword
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All keywords are defined in lower case
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Data type
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net
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reg
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parameter
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Data type - net (wire)
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Data type - reg
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A reg data type represents a variable in Verilog
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Type ”reg” variable stores values, but not necessarily a
FF (register)
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Are only assigned in an ”always” block task or function
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If a reg data type is assigned a value in an always block
that has a clock edge expression, a flip-flop is inferred
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Data type - reg
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By default, net and register are one-bit wide
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Data type - parameter
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Represents constants
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Declared by: parameter data_size = 5;
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Cannot be changed at run time
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Value Set
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Verilog has four value levels
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Operator Priority
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Module
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Module - example
module
name
module half_adder (
x,
y,
c,
port name
s
);
// port declaration
input x; // width: 1 bit
input y;
output c, s;
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// I/O type and data type
wire c;
wire s;
// functionality or structure
xor (s, x, y); // (out, in, ……)
and (c, x, y);
endmodule
Verilog
primitive
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Circuit design using
- Four kinds of model

Switch Level Model

Gate Level Model

Data Flow Model

Behavioral Model
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Example: Half adder
module half_adder (
//input
x,
y,
//output
c,
s
);
// port declaration
input x; // width: 1 bit
input y;
output c, s; Gate Level Model
// I/O type and data type
wire c;
wire s;
// functionality or structure
xor (s, x, y);
and (c, x, y);
x
S
half_adder
y
x
S
C
Behavioral Model
C
y
reg s,c;
always @(x or y)
begin
s=x^y;
c=x&y;
Data Flow Model
assign s=x^y;
assign c=x&y;
end
endmodule
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Example: Full adder (Gate Level Model)
module full_adder (x, y, z, S, C);
input x, y, z;
output S, C;
wire01
x
S
xor01
// internal nets/registers
wire wire01;
wire wire02;
wire wire03;
xor02
wire03
y
C
and01
and02
z
wire02
// functionality or structure
xor xor01(wire01, x, y);
and and01(wire02, x, y);
xor xor02(S, wire01, z);
and and02(wire03, wire01, z);
or (C, wire02, wire03);
endmodule
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Example: Full adder (2HA+1OR)
module full_adder (x, y, z, S, C);
input x, y, z; output S, C;
wire wire1, wire2, wire3 ;
// functionality or structure
// module instantiations
half_adder ha1(
//input
.x (x),
.y (y),
//output
.c (wire2),
.s (wire1)
);
half_adder ha2(
//input
.x (wire1),
.y (z),
//output
.c (wire3),
.s (S)
);
or (C, wire2, wire3);
endmodule
x
s
HA 1
y
z
wire1
S
s
HA 2
c
c
wire3
C
wire2
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Instantiation and port mapping

In order
// in half_adder.v
half_adder (x, y, c, s);
// in full_adder.v
half_adder ha1(x, y, wire2, wire1);
half_adder ha2(wire1, z, wire3, s);

By name
// in half_adder.v
half_adder (x, y, c, s);
// in full_adder.v
half_adder ha1(.x(x), .y(y), .c(wire2), .s(wire1));
half_adder ha2(.x(wire1), .y(z), .s(s), .c(wire3));
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Outline

IC Design Flow and FPGA

Introduction to HDL

Write Verilog code using Quartus II

Lab
2015/7/20
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Step by Step

Getting Started –

Start the Quartus II software
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Step by Step

Create a New Project –

Open New Project Wizard (File → New Project Wizard…)
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Step by Step

Specify the working directory and the name of the
project
可先新增資料夾
請記住!
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Step by Step


Select design files. Or click “Next” to skip this step
Specify device settings - (Here we use the VerLite Device
family)
EP1C6Q240C8
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Step by Step

Edit a Schematic File Open a new Verilog HDL file

(File → New → Verilog HDL File → OK)
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Step by Step

Write Verilog code
Top module name 一定要跟 Project name 相同 !!
1:
2:
3:
4:
//File Name：Half_Adder.v
module
Half_Adder(a, b, sum, carry);
input
a, b;
output
sum, carry;
5:
6:
7:
輸入(input)
被加數(a)
加數(b)
0
0
0
1
1
0
1
1
a
assign sum = a ^ b;
b
輸出(output)
和(sum)
進位(carry)
0
0
1
0
1
0
0
1
Half Adder
sum
carry
assign carry = a & b;
8:
9:
endmodule
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Step by Step

Compiling the Designed Circuit

(Processing → Start Compilation)
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Step by Step

Successful compilation
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Step by Step

Simulating the Designed Circuit
 Using the Waveform Editor (File → New → Vector
Waveform File)
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Step by Step

Simulating the Designed Circuit
 Use node finder to find all the pins (Edit → Insert →
Insert Node or Bus…)
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Step by Step

Simulating the Designed Circuit
 Selecting nodes to insert into the Waveform
Editor
沒跑出pin腳，表示你剛剛忘記compile
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Step by Step

Simulating the Designed Circuit
 Selecting nodes to insert into the Waveform
Editor
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Step by Step

Simulating the Designed Circuit

Select and edit waveform
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Step by Step

Simulating the Designed Circuit
 Setting of test values
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Step by Step

Performing the Simulation
 Modify default settings (Assignments → Settings… →
Simulator Settings → Functional → OK)
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Step by Step

Generate functional simulation netlist before
simulation (Processing → Generate Functional Simulation Netlist)
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Step by Step

Start simulation (Processing → Start Simulation
)
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Step by Step

The result of functional simulation
輸入(input)
被加數
加數(b)
(a)
0
0
0
1
輸出(output)
進位
和(sum)
(carry)
0
0
1
0
1
0
1
0
1
1
0
1
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Outline

IC Design Flow and FPGA

Introduction to HDL

Write Verilog code using Quartus II

Lab
2015/7/20
48
Lab I

Using Verilog to implement a 1-bit Full Adder

Simulation Result
z
y
x
S
C
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
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Lab I - Hint
 Hint (Gate Level Model)
wire01
x
S
xor01
xor02
wire03
y
C
and01
and02
z
wire02
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Lab II


Using Verilog to implement a 2-bit Full Adder
Simulation Result
z1
y1
x1 C1 y2
x2
S1
S2 C2
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
0
0
1
0
0
1
0
1
1
0
0
1
1
1
0
0
0
1
0
1
0
0
0
1
1
1
0
1
1
0
1
1
0
1
0
0
1
1
1
0
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
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Lab II - Hint
wire01
wire01
x1x
S1
S
xor01
xor02
wire03
wire03
y1y
and01
C
C1
and02
z1z
or01
Ref. Instantiation and port mapping
wire01
wire04
x
x2
xor01
xor03
wire02
wire02
xor04
S
S2
xor02
wire06
wire03
y2
y
z
X
C1
and01
and03
and02
and04
C
C2
or02
wire05
wire02
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Notice

請勿在桌面建立 Project 及請勿命名中文資料夾

Device family 請確認與 FPGA Chip 符合 (EP1C6Q240C8)

Top module name & Project name 需要一致

確認 module … endmodule 為keyword 變成藍色字體
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