Transcript Printed Wiring Board Fabrication

Printed Wiring Board Fabrication
Imaging
•
For feature sizes less than 200μm, use
photolithography process
1.
2.
3.
4.
5.
6.
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Clean surface
Apply photoresist
Expose photoresist
Develop photoresist image
Pattern transfer image (plating or etching)
Strip photoresist
Dry film photoresist for pattern formation
Liquid photoresists for precision work (less
than 50μm)
Drilling
• Purpose is to form an electrical connection between
layers and permit through-hole component mounting
• Typically use tungsten carbide drill bits at speeds of
50,000 to 100,000rpm
• Most common defects are:
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–
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Delamination - vibrational
Smear - thermal
Burr - sharpness
Debris - sharpness
• Drill smear is the most important factor for hole quality
• Drill smear occurs due to heating of the PWB by the drill,
which can cause epoxy-resin melting
Plating
• Metal deposition by electroless and electrolytic
processes
• Typically use copper with the following
requirements
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High electrical conductivity
Good mechanical strength
High ductility and elongation
Excellent solderability
Good tarnish and corrosion resistance
Good etchant resistance
• Also can add Sn, Sn-Pb, or Ni undercoating as a
solder barrier
Etching
• Typically chemical etching used (alkaline
ammonia, hydrogen peroxide-sulfuric acid,
cupric cholride)
• Process steps:
– Resist stripping
– Precleaning
– Etching
– Neutralization
– Water rinsing
– Drying
Single-sided PWB Fabrication
• Single layer process
shown
• Can either use:
– Photolithographic
process
• Higher precision
• Higher cost
– Screen printing
• Lower precision
• Lower cost
Double-sided PWB Fabrication
1. Holes drilled, deburred,
and cleaned
2. Panels prepared for
electroplating
3. Deposit, mask, expose,
and develop photoresist
(UV light)
4. Copper electroplating
5. Additional electroplating
(Sn-Pb) to protect and
improve quality of
surface
6. Strip photoresist
7. Solder reflow
Multilayer PWB Fabrication
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Pressing process to form
layers
Alignment is critical
Process steps:
1. Panels produced using doublesided etching from prepreg
laminates
2. Panels are laminated, pressed,
and cured
3. Additional drilling, electroplating
and etching as required
Four Layer PWB Example
Solder Masks
•
Three primary types of
solder resist masks:
1.
2.
3.
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•
Screen-printed
Dry film
Liquid photoimageable
(LPI)
Dry film and LPI
produce finer features
than screen-printed
Protection of exposed
surfaces using finishes
Finish
Typical
Thickness
Features
Electroplated
Ni + matte Sn
7.5μm Sn
over 5μm Ni
Solderable surface and
good shelf life
Electroplated
Ni + hard Au
0.75-1.25μm
Au over 5μm
Ni
Excellent corrosion
resistance, shelf life,
hardness and wear
resistance.
Electroplated
Ni + soft Au
0.75-1.25μm
Au over 5μm
Ni
Excellent corrosion
resistance and shelf life,
fair wear resistance
Electroless
plated Ni +
immersion gold
0.02-0.1μm
Au over
4.5μm Ni
Excellent corrosion
resistance, solderability,
and shelf life
Hot-air solder
leveling
(HASL)
1.5-5μm SnPb
Excellent solderability,
good shelf life
Organic
solderability
preservative
(OSP)
0.2-0.5μm
Excellent solderability,
surface coplanarity and
hole size uniformity, and
good shelf life
Limitations on PWB Process
• New products
require higher
pad densities
• Drilled hole
technology
becomes too
expensive
• Microvia is the
solution
Microvias
•
Fabrication processes:
1. Laser drilling
2. Plasma or RIE
3. Photolithography
•
Advantages for high
volume production:
1. Increased circuit density
2. Advanced packages
enabled
3. Better electrical
performance
4. Improved reliability than
drilled holes
5. Improved thermal
conductance
6. Lower PWB cost
Microvia Generation
1.
Photovia
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2.
Plasmavia (PEV)
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3.
Very flexible process
Can generate many different
geometries
Typically 60-90μm diameter
Laservia
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4.
Utilizes photolithography
Requires photosensitive
permanent dielectrics
Economical for mass
production
Nd:YAG, CO2, UV excimer
Paste-via
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Cheap, but less reliable
Laservia is the best overall microvia process
• Direct CO2 laser drilling is
leading throughput and quality of
holes
• 20,000 holes/min/head
Microvia Board Technologies
•
Three major technologies
1. Surface Laminar Circuitry (SLC) or Build-Up
Technology
2. All Layer Internal Via Hole (ALIVH)
Technology
3. Buried Bump Interconnection Technology
(B2IT)
Build-Up Technology
• Can use photosensitive
dielectrics for photovias or
use lasers to drill vias
• Copper lines can be
spaced as close as 20μm
wide
• Lastly, gold plating is used
for wire bondable surface
finish
All Layer Internal Via Hole (ALIVH) Process
• Invented by
Matsushita in Japan
• Used primarily for cell
phone boards
• Uses epoxy-aramid
prepregs with laser
drilled vias, which are
filled with copper
paste
Buried Bump Interconnection Technology
(B2IT)
• Invented by Toshiba
in Japan
• Uses silver paste
bumps to punch holes
in dielectric or
prepreg
PWB Market
Expected growth of PWBs
and microvias
PWB Trends
Feature size and pitch
decrease as number of
pins increases
Summary and Future Trends
• PWB Fabrication process (Imaging, Drilling, Plating, and
Etching)
• Different board fabrication processes (Single-sided,
Double-sided, and Multilayer)
• Microvia generation (Photovia, Plasmavia, and Laservia)
• Microvia board fabrication (Build-up, ALIVH and B2IT)
• Trade-offs (cost, reliability, quality of contacts, dielectric
properties, feature sizes, etc.)