KEK SOI

技術による光、放射線 ピクセル検出器

@ Dec. 18, 2010 二重ベータ崩壊研究懇談会 モンタナリゾート岩沼 KEK 新井康夫 [email protected]

http://rd.kek.jp/project/soi/ 1

OUTLINE

1. Introduction 2. SOI Pixel Process 3. Developed Pixel Detectors 4. Process Improvements 5. Summary 詳しくは 

Silicon-On-Insulator (SOI) Wafer SmartCut (1991) Michel. Bruel Leti( 仏） ) Layer Transfer 3

SOI Pixel

検出器 Charged Particle KEK 測定器開発プロジェクト • 高比抵抗Si基板と低比抵抗Si基板を絶縁層を介して張合わせ。 • 高比抵抗部に不純物implant、p-n junctionを生成。 • 絶縁層(BOX: Buried Oxide)に穴を開けセンサーと回路を接続。

Metal contact & p+ implant

1st Al Handle Wafer Copyright 2007 Oki Electric Industry Co.,Ltd 6

SOI Pixel検出器の特徴 • 余分な物質が少なく、多重散乱をおさえられる。 • 電極容量が小さく、少ない電荷 ( 薄いセンサー）で大きな S/N が得 られる。 • 複雑な信号処理回路を各ピクセルに持たせられる。 • 高レート、高速読み出し、ローカルメモリー等が可能。 • 機械的接合がなく、高分解能化、低価格化が望める。 • 産業界の標準 プロセスを基本に 開発。

Possible Radiation Detection Schemes X−ray, Visible Light, Near Infra Red, ...

Thin detector(~50um).

Low mass Multi layer by adding conversion layer 8

Process SOI wafer Backside OKI 0.2 m m FD-SOI Pixel Process 0.2

m m Low-Leakage Fully-Depleted SOI CMOS (OKI) 1 Poly, 4 (5) Metal layers, MIM Capacitor, DMOS option Core (I/O) Voltage = 1.8 (3.3) V Diameter: 200 mm  , Top Si : Cz, ~18  -cm, p-type, ~40 nm thick Buried Oxide: 200 nm thick Handle wafer: Cz ~700 or FZ~10k  -cm , 720 m m thick Thinned and deposited with Al (200 nm).

An example of a SOI Pixel cross section 9

Integration Type Pixel (INTPIX) 

V sense



Q C

 0.6

fC

8

fF

 70

mV

b -ray Size : 14 m m x 14 m m with CDS circuit

Integration Type Pixel (INTPIX4) Largest Chip so far.

15 mm 10 mm 17x17 m m, 512x832 (~430k ） pixels 、 13 Analog Out 、 CDS circuit in each pixel.

Counting Type Pixel (CNTPIX5)

Energy selection and counting hit in each pixel 5 x15.4 mm 2 72 x 272 pixels 64um x 64 um pixel 3 side buttable 12

CNTPIX5 Pixel Layout 64x64 um 2 ピクセル内 にすべての エレクトロニ クスを内蔵 ~600 Tr/pix x 72 x 212 = 10 M Trs 13

X-ray Measurement

ｓ

with SOI pixel

5mm 高分解能 ピクセル内でエネルギー 分離が可能 14

Buried p-Well to suppress back gate effect

One of the major issues in realizing SOI pixel sensor is Back Gate Effect. To deplete the sensor Si, we have to apply high voltage (~100V) from back. This back voltage affect the characteristics of the transistor.

MOS Tr Vback 15

Buried Oxide (BOX)

Buried p-Well (BPW)

Substrate Implantation BPW Implantation SOI Si Pixel Peripheral P+ • Cut Top Si and BOX • High Dose BPW • Keep Top Si not affected • Low Dose • Suppress the back gate effect.

• Shrink pixel size without loosing sensitive area.

• Increase break down voltage with low dose region.

• Less electric field in the BOX which promote recombination of electron and hole, thus improves radiation hardness.

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NMOS

Vback Effect to I

d

-V

g w/o BPW with BPW=0V back channel open shift Back gate effect is completely suppressed by the BPW.

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Nested BNW/BPW Structure implant • Signal is collected with the deep Buried P-well.

• Back gate and Cross Talk are shielded with the Buried N-well.

• Test chip is under process.

こういった複雑な構造も可能に 18

MPW (Multi Project Wafer) runs We are operating our own MPW runs Twice per Year by including many designs from other laboratory.

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KEK SOI Pixel MPW run Users/Collaborations KEK, Tsukuba Univ., Tohoku Univ., Kyoto Univ., Kyoto U. of Education, Osaka Univ., JAXA/ISAS, RIKEN, AIST (Japan) LBNL, FNAL, Univ. of Hawaii (U.S.A.) INP Krakow, INFN Padova, Louvain-la-Neuve Univ., Universität Heidelberg (Europe) IHEP China, Budker Institute of Nucl. Phys. (Asia) Supporting Companies OKI Semiconductor Co. Ltd. , OKI Semiconductor Miyagi Co. Ltd. , T-Micro Co. Ltd. (ZyCube), Rigaku Co. Ltd.

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Summary

• SOI

ピクセルは理想的な構造を 持ったモノリシック放射線検出器。

• Multi Project Wafer run

を定期的に行う事で、様々な 応用に向けた検出器の設計が進んでいる。

•

より複雑なセンサー構造、高比抵抗化、薄型化、極低 温応用、３次元実装等多くの

R&D

が進んでいる。

•

興味のある方はぜひご参加下さい。 21

Supplement 22

Total Ionization Dose effect can be compensated by back bias Leak Current and V Th resumes to nearly original value by biasing back side even after 100Mrad.

Vback= 0 -10 -20 -30V

10 15 p/cm 2 (~100 Mrad)

before irradiation

10 15 p/cm 2 (~100 Mrad)

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e. Double SOI Layer wafer Increase radiation hardness by compensating Oxide/Interface Trap charge with middle layer bias.

circuit sensor additional conduction layer Shield sensors from circuit 24

Concentration Profile of Implanted Dopant By adjusting Implant Energy and Flux, we can create p-layer under the BOX without changing the active density.

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FZ-SOI Wafer Process During the conventional SOI process, many slips were generated in the 8’’ FZ-SOI wafer.

Before Oxidation Conventional SOI Process Resistivity is increased 10 times high!

Improved SOI Process Slips We optimized the process parameters, and succeeded to perform the process without creating many slips.

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FZ-SOI Wafer Depletion FZ-SOI wafer of 260um width is fully depleted @22V while CZ-SOI wafer requires more than 250V.

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Box (Buried Oxide) (200 nm)

SOI Pixel Process Flow

SOI (40 nm) Handle Wafer Handle Wafer p+ n+ 650um Al Handle Wafer n+ p+ 50~650um

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