Transcript Chapter 10
CMOS Analog Design Using All-Region MOSFET Modeling Chapter 10 Fundamentals of sampled-data circuits CMOS Analog Design Using All-Region MOSFET Modeling 1 MOS sample-and-hold circuits Basic MOS sample-and-hold circuit (the circuit implements a trackand-hold function, but we adopt the term sample-and-hold, the most commonly used in the literature) CMOS Analog Design Using All-Region MOSFET Modeling 2 Thermal noise in S/H Equivalent circuit of the S/H with the switch on and vi = 0. Power spectral density of the noise voltage across the capacitor CMOS Analog Design Using All-Region MOSFET Modeling 3 Idealized sampling s(t ) (t nTs ) xs x(t )s(t ) 1 X s j 2 f X j 2 f jm2 f s Ts m CMOS Analog Design Using All-Region MOSFET Modeling 4 Aliasing of thermal noise The resistor noise power spectral density is multiplied by 2 fNB/fs: (2kTRON ). 2 f NB 4kTRON 1 kT fs fs 4RON C Cf s The fully aliased thermal noise in the (useful) Nyquist bandwidth -fs/2 < f < fs/2 is 2 vCN f 2fNB kT kT fs Cf s C fs f Simplified representation of the aliasing of thermal noise due to sampling for the case 2fNB/fs = 6. CMOS Analog Design Using All-Region MOSFET Modeling 5 Thermal vs. quantization noise /2 2 rms e 2 1 e de 12 /2 2 kT 2 C 12 2B C 12kT VFS Number of bits (B) 8 12 14 16 20 2 Capacitance (C) 3.3 fF 0.83 pF 13.3 pF 213 pF 55 nF VFS= 1 V and T=300 K Quantization error of digitized analog waveform. VFS is the full-scale voltage range and Δ is the size of the LSB CMOS Analog Design Using All-Region MOSFET Modeling 6 Switch on-resistance gon, N gon,P gon, N gon, P 0 VDD VDD VT 0, P nP VDD VT 0, N nNt VDD Vin Variation of the on-conductance of the nMOS, pMOS, and CMOS switches with the input voltage. Illustration of the distortion produced by the inputdependent delay of the MOS S/H in the tracking mode CMOS Analog Design Using All-Region MOSFET Modeling 7 Linearization of the MOS sampling switch Linearized S/H with output buffer Sampling instant variation (a) ordinary S/H; (b) linearized S/H CMOS Analog Design Using All-Region MOSFET Modeling 8 Charge injection by the switch - 1 Ts 5RON CH 2 fs RON 1 10 RON CH QI For V 2CH RON 1 W QI L L2 QI QI 1 V fs 10RON CH 10L2CH 5L2 For ΔV = 1mV, calculate the maximum clock frequencies for effective channel length of 1 µm, 0.316 µm and 100 nm µ = 500 cm2/V·s Answer: fs : 10 MHz, 100 MHz, and 1 GHz, for 1 µm, 0.316 µm, and 100 nm channel lengths, respectively. CMOS Analog Design Using All-Region MOSFET Modeling 9 Charge injection by the switch - 2 Charge injection cancellation techniques: (a) short fall time of the clock and half-sized dummy switches, (b) fully-differential structure CMOS Analog Design Using All-Region MOSFET Modeling 10 Low-voltage S/H circuits - 1 On-conductance of a CMOS switch for two different supply voltages: (a) VDD = 5V and (b) VDD = 1.5 V CMOS Analog Design Using All-Region MOSFET Modeling 11 Low-voltage S/H circuits - 2 (a) Available output swing obtained by dcshifting the input signal applied to the n- and p-MOS switches (VDSsat is the voltage margin to either VDD or ground required for the proper operation of the blocks, e.g., amplifiers, connected to the switches); (b) Low-voltage S/H that provides dc bias for proper operation of both switches CMOS Analog Design Using All-Region MOSFET Modeling 12 Low-voltage S/H circuits - 3 Bootstrapped MOS switch: (a) Simplified schematic and (b) Input (source) and clock (gate) signals CMOS Analog Design Using All-Region MOSFET Modeling 13 Jitter analysis T is a random variable the standard deviation of which is called (aperture) jitter a, measured in (rms) seconds. Typical clocks: jitter of 100 ps rms, high quality clocks jitter of 1 ps rms. the signal-to-noise (SNR) of the S/H due to clock jitter is given by 1 VFS 2 2 2 20 log SNR 10 log10 10 2 a f sVFS 2 CMOS Analog Design Using All-Region All Region MOSFET Modeling 2 f s a 14 Resolution vs. sampling rate in A/D Resolution, in number of bits, as stated by the manufacturer, versus sampling rate, for A/D converters implemented in silicon CMOS Analog Design Using All-Region MOSFET Modeling 15 Basics of switched-capacitor (SC) filters q1 C1vA q2 C1vB q q1 q2 C1 vA vB iav q / T C1 / T vA vB Thus, on average, the switched capacitor behaves as a resistor with its resistance value given by R1 T / C1 1/ C1 f s CMOS Analog Design Using All-Region MOSFET Modeling 16 First-order low-pass SC filter CR vR tn - T / 2 CvO tn - T / 2 CR C vO tn vo tn T / 2 vo tn T vR tn T / 2 vR tn T CRvR tn T Cvo tn T CR C vo tn CRVR2 z 1 CVo2 z 1 CR C Vo2 Vo2 CR z 1 2 VR CR C 1 z 1C /(CR C ) CMOS Analog Design Using All-Region MOSFET Modeling 17 Switched-capacitor integrators – 1 (a) Continuous-time and (b) parasitic-sensitive switched-capacitor integrators. jT /2 T / 2 C C1 1 e jT 1 H z e jT C2 1 e C2 jT sin T / 2 H z e jT T 1 C1 1 C2 jT CMOS Analog Design Using All-Region MOSFET Modeling 18 Switched-capacitor integrators – 2 2 v1 1 1 C1 V21 z C1 z 1/ 2 H12 z 2 V1 z C2 1 z 1 C2 2 v2 (a) 1 v1 2 1 C1 2 V21 z C 1 H11 z 1 1 V1 z C2 1 z 1 C2 v2 (b) V22 z C1 z 1 H 22 z 2 V1 z C2 1 z 1 V22 z C1 z 1/ 2 H 21 z 1 V1 z C2 1 z 1 (a) Non-inverting and (b) inverting parasitic-insensitive integrators CMOS Analog Design Using All-Region MOSFET Modeling 19 SC circuits as charge processors - 1 (a) Elementary charge mirror and (b) Basic SC signal processing blocks qA CAv CA0 f v v qB CBv CB0 f v v qB CB 0 area(CB ) qA CA0 area(CA ) CMOS Analog Design Using All-Region MOSFET Modeling 20 SC circuits as charge processors - 2 Third-order SC filter qI nT T / 2 CE 0 C qA nT F 0 qB nT C A0 CB 0 qA nT qA nT T CG 0 qA nT T qB nT qB nT T C A0 CH 0 C C C qB nT J 0 qC nT D 0 qA nT D 0 qA nT T CB 0 CC 0 C A0 C A0 qC nT qC nT T CMOS Analog Design Using All-Region MOSFET Modeling 21 SC circuits as charge processors - 3 Signal-flow graph of the third-order SC filter CMOS Analog Design Using All-Region MOSFET Modeling 22 SC circuits as charge processors - 4 Measured output waveforms at (a) an intermediate node and (b) output node of an SC filter implemented with nonlinear capacitors, with the exception of the linear input and output capacitors CMOS Analog Design Using All-Region MOSFET Modeling 23