Transcript 23-I2C - 로봇SW교육원

UNIT
23 I2C
로봇 SW 교육원
조용수
학습 목표
•
•
•
•
I2C
I2C Protocol 구조
N051 I2C 동작
I2C Register
2
I2C Bus
3
• Inter Integrated Circuit Bus
• TWI : Two Wire Interface
• Phillips 에서 제안한 규격으로 2선만을 이용하여 시
리얼 전송하는 프로토콜
– SCL : I2C Clock
– SDA : I2C Data
• I2C 는 1:N 통신이 가능하며 , 각각 디바이스는
Address 를 가지고 있다.
I2C Protocol 구조
• Normally, a standard communication consists of 4 sta
ges:
– START or Repeated START signal generation
– Slave address transfer
– Data transfer
– STOP signal generation
SCL
1
2
7
8
9
1
2
3-7
8
9
D0
NACK
ACK
P
SDA
A6
S
or
Sr
MSB
A5
A4 - A1
A0
R/W
LSB
ACK
D7
MSB
D6
D5 - D1
LSB
P
or
Sr
Sr
Data Transfer
When successful slave addressing has been achiev
ed, the data transfer can proceed on byte-by-byte ba
sis in the direction specified by the R/W bit.
The data length is based on actual application.
SCL
1
2
7
8
9
1
2
3-7
8
9
D0
NACK
ACK
P
SDA
A6
S
or
Sr
MSB
A5
A4 - A1
A0
R/W
LSB
ACK
D7
MSB
Data transfer stage
(example 1 byte data)
5
D6
D5 - D1
LSB
P
or
Sr
Sr
Acknowledge
Acknowledge
Position
SCL FROM
MASTER
1
2
DATA OUTPUT BY
TRANSMITTER
DATA OUTPUT BY
RECEIVER
clock pulse for
acknowledgement
8
9
NACK: High lev
el
not acknowledge
S
acknowledge
START
condition
ACK: Low level
Each transferred byte is followed by an ACK or a NACK at 9th
clock.
6
I2C Read / Write Protocol 구조
• I2C Writ
• I2C Read
7
N051 I2C Bus
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•
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8
Compatible with Philips I2C standard.
Support Master/Slave mode
Support 7 bit addressing mode
Built-in a 14-bit time-out counter to avoid the I2C b
us hang-up.
• Multiple address recognition ( Four slave address
with mask option)
I2C Status
9
I2C Register
10
I2C Register
11
I2C Register
12
I2C Register
13
I2C Register
14
I2C Register
15
I2C Register
16
I2C Register
17
I2C Register
18
I2C Register
19
I2C Register
20
I2C Register
21