Transcript DAC07.ppt

Transition Delay Fault Test Pattern
Generation Considering Supply
Voltage Noise in a SOC Design
Nisar Ahmed and M. Tehranipoor
University of Connecticut
Vinay Jayaram
Texas Instruments, TX
Overview
Objective
Prior Work
Test Strategy using Statistical IR-drop Analysis
Fault List Manipulation
Power Model
Switching Cycle Average Power (SCAP)
SCAP Calculator
Pattern Generation Framework
Experimental Results
Conclusions
2/7
Objective
High switching activity during test compared to
functional operation
Increased sensitivity of VDSM designs to supply noise
IR-drop during at-speed test: A BIG CONCERN
Present ATPG tools are supply noise unaware
Targets as many faults as possible per pattern
Random filling of X’s during ATPG
Increases switching activity of test patterns
How to generate IR-drop tolerant patterns without
significantly increasing number of patterns?
3/7
IR-drop Effects?
Delay Failure
An excessive IR-drop can increase the delay of
targeted paths
Logic Failure
An excessive IR-drop can significantly reduce the
voltage reaching a device -- may function
unpredictably
Question:
What is the impact of IR-drop on long and short paths
Answer:
Slack of a path and number of switching define how
tolerant a path is to IR-drop
4/7
Prior Work
IR-drop issue during at-speed test [Saxena, ITC03]
Static Verification of Test Vectors for IR-drop Failure
[Kokrady, ICCAD03]
Power Supply Noise Analysis in Test Compaction
[Wang, ITC05]
Preferred-Fill [Remersaro, IEEE D&T 07]
Low-capture TDF pattern generation [Wen, VTS05, VTS06]
Faster-than-at-speed test considering IR-drop [Ahmed,
ICCAD03]
5/7
Contributions
Novel Power model to measure the average power
during at-speed test
Called Switching cycle average power (SCAP)
Consider both the length of paths affected by each
pattern and the number of transitions
Pattern generation procedure:
Set SCAP threshold
Perform TDF pattern generation
Identify high IR-drop patterns using SCAP
Replace them with IR-drop tolerant patterns
6/7
SOC Design
Dual processor SOC (Cadence Design ‘TurboEagle’)
6 Blocks connected by AMBA bus
SOC Design Floorplan
200K gates, 23K scan cells
16 scan chains
Wire-bond package
37 VDD (VSS) pads
0.18 nm technology
6 Clock Domains
Bi-directional pins work in
input mode during test
7/7
Test Strategy
What combination of blocks in each clock domain need to
be tested together to reduce both test time and IR-drop?
Identify dominant clock domains
Clock domain with very high number of controlled scan
flip-flops
Clock Domain # Scan Cells
clkA
clkB
clkC
clkD
clkE
clkF
17966
1165
1673
724
1560
142
Frequency
[MHz]
50
100
50
25
25
25
Blocks
Covered
B1-B6
B1
B3
B6
B6
B2
clkA domain will observe high switching activity and IR-drop
8/7
Test Strategy (cont.)
IR-drop depends on
Design parameters:
Power and ground network
Number of VDD/VSS pads and their placement
Package type (Wire-bond or flip-chip)
Size and placement of decoupling capacitance
Pattern dependent factors:
Switching activity
Time frame of activity
IR-drop reduction depends on reducing switching
activity in design blocks observing high IR-drop
(based on the above design parameters)
Statistical IR-drop analysis considers all design parameters
9/7
Statistical IR-drop analysis
Vector-less approach to estimate functional IR-drop
Assumptions:
Uniform activity over the entire design region
Switching time frame = clock period
Underestimates average functional IR-drop and power
Non-uniform switching activity
Most activity occurs during early cycle period
Delay test patterns have varying switching time frame
window (STW)
Time span during which all activity occurs
IR-drop inversely proportional to switching time-frame window (STW)
10/7
Statistical IR-drop analysis (cont.)
What is an average switching time-frame window to
estimate average functional IR-drop and power ?
Procedure:
Generate transition fault test patterns
Measure time-span of all switching activity during
launch-to-capture window
Average switching time frame = Half cycle period
Statistical IR-drop analysis for the avg. switching time
frame window (STW)
Identifies design blocks observing high IR-drop
Avg. power threshold to identify high IR-drop
delay test patterns
11/7
Statistical IR-drop analysis (cont.)
Full cycle period
Avg. Switching
Power [mW]
Half cycle period
Worst Avg.
IR-drop [V]
VDD
VSS
Avg. Switching
Power [mW]
Worst Avg.
IR-drop [V]
VDD
VSS
B1
20.8
0.033
0.033
30.6
0.034
0.034
B2
34.5
0.035
0.036
87.2
0.043
0.044
B3
12.9
0.028
0.028
17.6
0.029
0.029
B4
4.8
0.019
0.019
9.3
0.020
0.020
B5
108.6
0.076
0.076
204.9
0.119
0.120
B6
63.8
0.045
0.045
114.6
0.051
0.050
Chip
265.2
0.077
0.077
404.5
0.126
0.125
1. Avg. switching power is almost doubled when STW is halved
2. Worst avg. IR-drop does not change much when STW is halved (except B5)
3. Blocks B5 and B6 consume high switching power and observe high IR-drop
12/7
Statistical IR-drop analysis (cont.)
2. Worst avg. IR-drop does not change much when STW is halved (except B5)
3. Blocks B5 and B6 consume high switching power and observe high IR-drop
Blocks B1-B4 and B6 are on
the chip boundary
Experience low IR-drop
than B5
B1-B4 can be tested together
B5 and B6 are tested
individually
More focus needed to reduce
IR-drop in block B5
13/7
Fault List Manipulation for ATPG
High switching activity during test
Targets as many faults as possible per pattern
Break the fault list and feed to ATPG tool
{B1-B4}, {B5}, {B6}
Random filling of X’s during ATPG
Use appropriate fill-X options to reduce activity (fill-0
option as it gave best results)
While testing {B1-B4}, use fill-X option in other
blocks to reduce activity in them
14/7
Power Model (SCAP)
Average IR-drop directly relates to average power
Cycle average power (CAP)
Power measured over entire cycle period
Switching cycle average power model (SCAP)
Measured over switching time frame window (STW)
Clock Network Switching
CAP = ∑(Ci * VDD2)
T
VDD2)
SCAP = ∑(Ci *
STW
ATE clock
T
FF clock
STW (P1)
Scan Enable
STW (P2)
15/7
SCAP Model Validation
SCAP(P1) > SCAP(P2)
SCAP in block B5 for clkA
domain delay test patterns
SCAP threshold from
statistical IR-drop analysis
P1
P2
SCAP is a good power model to
represent average IR-drop
16/7
SCAP Calculator
Design Test
(.v) Patterns SDF
PLI routine to measure
power during launch-tocapture window
Physical
Design (DEF)
Avoids huge VCD file
generation for large designs
SCAP = ∑(Ci * VDD)2
STW
SCAP
Calculator
VCS
Pattern
Power
Profile
SDF – Standard delay format (Timing Information)
VCS – Gate level simulator (Synopsys)
PLI – Programmable language Interface
STAR-RXCT – Extraction tool (Synopsys)
PLI
STAR-RXCT
Parasitics
(SPEF)
Instance
Capacitance
extractor
17/7
Pattern Generation Framework
Pattern Generation Procedure:
Preprocessing Phase:
Statistical IR-drop analysis
Identify design blocks with high IR-drop and power surge
Fault list manipulation for ATPG
Step 1: Run ATPG for each fault subset at a time
Step 2: Measure SCAP and exclude high IR-drop
Patterns (short-listed patterns)
Step 3: Fault Simulate short-listed patterns  fault list
Step 4: Run ATPG for this fault list
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Pattern Generation Framework
Pre-processing phase
Statistical IR-drop
Analysis
Commercial
ATPG tool
Fault List
Manipulation
Fault List
Subsets
ATPG
FS
Pattern
Set
Fault
List
SCAP Calculator
Thr
If
SCAP>Thr
?
No
Yes
Short-listed
Patterns
Exit
19/7
Experimental Results
Comparison of conventional ATPG and the new pattern
generation procedure
Random fill for don’t-care bits for conv. pattern set
Slight increase in pattern volume
644 extra patterns generated
20/7
Results (cont.)
Block B5
Block B5 in quiet
state during {B1-B4}
and {B6} fault list
ATPG
Fill-0 option used
during ATPG to
reduce activity
21/7
Conclusion
New pattern generation procedure for IR-drop tolerant
pattern generation
Switching cycle average power (SCAP) model for
identifying high IR-drop patterns
Considers both switching capacitance and time
frame of activity
PLI based SCAP calculator
Efficient way to measure SCAP during launch-tocapture window
22/7