Transcript VTS07-version02.ppt

Supply Voltage Noise Aware
ATPG for Transition Delay
Faults
Nisar Ahmed and M. Tehranipoor
University of Connecticut
Vinay Jayaram
Texas Instruments, TX
Overview
Objective
Prior Work
Statistical IR-drop Analysis
Power Model
Switching Cycle Average Power (SCAP)
SCAP Calculator
Pattern Generation Framework
Experimental Results
Conclusions
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Objective
High switching activity during test compared to
functional operation
Increased sensitivity of VDSM designs to supply noise
IR-drop during at-speed test: A BIG CONCERN
Present ATPG tools are supply noise unaware
Targets as many faults as possible per pattern
Random filling of X’s during ATPG
Increases switching activity of test patterns
How to generate IR-drop tolerant patterns without
significantly increasing number of patterns?
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IR-drop Effects?
Delay Failure
An excessive IR-drop can increase the delay of
targeted paths
Logic Failure
An excessive IR-drop can significantly reduce the
voltage reaching a device -- may function
unpredictably
Question:
What is the impact of IR-drop on long and short paths
Answer:
Slack of a path and number of switching define how
tolerant a path is to IR-drop
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Prior Work
IR-drop issue during at-speed test [Saxena, ITC03]
Static Verification of Test Vectors for IR-drop Failure
[Kokrady, ICCAD03]
Power Supply Noise Analysis in Test Compaction
[Wang, ITC05]
Preferred-Fill [Remersaro, IEEE D&T 07]
Low-capture TDF pattern generation [Wen, VTS05, VTS06]
Faster-than-at-speed test considering IR-drop [Ahmed,
ICCAD03]
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Contributions
Novel Power model to measure the average power
during at-speed test
Called Switching cycle average power (SCAP)
Consider both the length of paths affected by each
pattern and the number of transitions
Pattern generation procedure:
Set SCAP threshold
Perform TDF pattern generation
Identify high IR-drop patterns using SCAP
Replace them with IR-drop patterns
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Case Study
ITC’99 benchmark (b19)
200K gates, 6642 scan cells
8 scan chains
Power/Ground Distribution Network
4 VDD (VSS) pads
0.18 nm technology
Frequency = 142MHz
Power rings Width = 20um
Stripes Width = 10um
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Statistical IR-drop analysis
Vector-less approach to estimate IR-drop analysis
Assumptions:
Uniform activity over the entire design region
Switching time frame = clock period
20% Net toggle activity
2.8% voltage drop in VDD network
4.5% voltage drop in VSS network
Underestimates average functional IR-drop and power
Non-uniform switching activity
Most activity occurs during early cycle period
IR-drop inversely proportional to switching time-frame window
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Statistical IR-drop analysis (cont.)
What is an average switching time-frame window to
estimate average functional IR-drop and power ?
Procedure:
Generate transition fault test patterns
Measure time-span of all switching activity during launchto-capture window
Average switching time frame = Half cycle period
Avg. Switching
Power [mW]
Full cycle period
96.3
Half cycle period
190.6
Avg. IR-drop [V]
VDD
VSS
0.05
0.084
0.11
0.162
Functional power threshold to identify high IR-drop test patterns
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Power Model (SCAP)
Average IR-drop directly relates to average power
Cycle average power (CAP)
Power measured over entire cycle period
Switching cycle average power model (SCAP)
Measured over switching time frame window (STW)
Clock Network Switching
CAP = ∑(Ci * VDD2)
T
VDD2)
SCAP = ∑(Ci *
STW
ATE clock
T
FF clock
STW (P2)
Scan Enable
STW (P1)
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Power Model (SCAP) (cont.)
Pattern P1 and P2
Almost same switching activity
Different switching time frame window (STW)
P2 has smaller STW
SCAP(P2) > SCAP(P1)
IR-drop effects on VDD
and VSS during pattern
P1 and P2 application
within 7ns capture
window.
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Power Model (SCAP) (cont.)
SCAP(P2) > SCAP(P1)
ITC’99 benchmark (b19)
P2
P1
Switching time frame window (STW) is an important parameter
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SCAP Model Validation
Another example:
Cadence SOC Design (Turbo Eagle)
P1
P2
SCAP is a good power model to
represent average IR-drop
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SCAP Calculator
Design Test
(.v) Patterns SDF
PLI routine to measure
power during launch-tocapture window
Physical
Design (DEF)
Avoids huge VCD file
generation for large designs
SCAP = ∑(Ci * VDD)2
STW
SCAP
Calculator
VCS
Pattern
Power
Profile
SDF – Standard delay format (Timing Information)
VCS – Gate level simulator (Synopsys)
PLI – Programmable language Interface
STAR-RXCT – Extraction tool (Synopsys)
PLI
STAR-RXCT
Parasitics
(SPEF)
Instance
Capacitance
extractor
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Pattern Generation Framework
With X-fill options
Statistical IR-drop
Analysis
Commercial
ATPG tool
ATPG
FS
Pattern
Set
Fault
List
Pattern Generation Procedure:
Step 1: Run ATPG for all faults
Step 2: Exclude high IR-drop Patterns
(short-listed patterns)
Step 3: Fault Simulate for Short-listed
patterns  fault list
Step 4: Run ATPG for this fault list
SCAP Calculator
Thr
If
SCAP>Thr
?
No
Yes
Short-listed
Patterns
Exit
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Experimental Results
Conventional transition fault pattern set
Random fill option for don’t-care bits
2360 patterns generated
VDD network
SCAP threshold =
20% toggle activity
over avg. switching
time frame window
VSS network
860 patterns with SCAP value above threshold
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Results (cont.)
New patterns generated with fill-0 and fill-1 options for faults
exclusively detected by short-listed patterns
Fill-0 generates 957 low-power patterns instead of 860 patterns
with high SCAP value
97 extra patterns but significantly reduces the SCAP value
Fill-0 option
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Results (cont.)
Fill-1 option
Fill Adjacent
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Results (cont.)
Comparison of conventional ATPG and the new
pattern generation procedure
Slight increase in pattern volume
4% increase in number of patterns
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Conclusion
New pattern generation procedure for IR-drop tolerant
pattern generation
Switching cycle average power (SCAP) model for
identifying high IR-drop patterns
Considers both switching capacitance and time
frame of activity
PLI based SCAP calculator
Efficient way to measure SCAP during launch-tocapture window
20/7