Transcript [ppt]

Extension of Asynchronous
Design Automation Tools
Michael Boyer
Advisor: Cherrice Traver
Steinmetz Symposium 2005
Introduction
• Synchronous (clocked)
• Clock skew
• Asynchronous (self-timed)
Advantages of Asynchronous
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No clock skew problem
Increased power efficiency
Increased performance
Greater tolerance of variation in operating
conditions
• Greater frequency distribution of
electromagnetic noise
• Component modularity
Real-World Examples
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Amulet 1, 2e, 3, 3i
Oticon DigiFocus hearing aid
Philips 80C51 microcontroller
Intel RAPPID Project
Phased Logic (PL)
• Automated translation
• Two phase LEDR signaling
E
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E
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E
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Liveness and Safety
• PL synthesis algorithm
– Guarantees liveness and safety
• Token abstraction
Coarse-Grained PL
• Wrap logic blocks with PL circuitry
• Logic blocks:
– Barrier blocks
– Through blocks
• Speed-up techniques:
– Time borrowing
– Early evaluation
Wrapper Circuit
VHDL Modeling
• New models:
– Wrapper models
– Environment models
• Assumptions
• Testing
ATACS
• Automatic Timed Asynchronous Circuit
Synthesis (ATACS)
• Automated verification:
– Hazard checking
Verification Example
100-200 ps
Results
Wrapper for Through Blocks with Time Borrowing:
min(D1, D2, D3, D4) + min(D5) ≥ max(C1) + max(xorG) + max(D-latch) – min(C2) – min(xorC) – min(DFF)
min(D1, D2, D3, D4) + min(D5) ≥ max(compute) + max(D-latch) – min(C2) – min(xorC) – min(DFF)
Wrapper for Through Blocks without Time Borrowing:
min(D1, D2, D3, D4) ≥ max(compute) + max(D-latch) – min(nC2) – min(DFF) – min(nC1)
Wrapper for Barrier Blocks without Early Evaluation:
min(D1, D2, D3, D4) ≥ max(compute) + max(Data DFF setup time) – min(nC)
Future Work
• Include results in mapping tool
• Use mapping tool to compare PL to
synchronous
• Implement PL in hardware
Acknowledgements
• Cherrice Traver, Union College
• Chris Myers, University of Utah
• Bob Reese, Mississippi State University
• IBM/SRC
Questions?